Memory lookup computing mechanisms
According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.
1 . A method comprising:
receiving, by a logic device, a result of a first operation stored on a memory device; and
performing, by the logic device, a second operation using the result of the first operation stored on the memory device,
wherein the result of the first operation is retrieved using a first floating point input value and a second floating point input value, the first floating point input value and the second floating point input value being used as addresses of the result of the first operation on the memory device.
2 . The method of claim 1 , wherein the first operation comprises:
retrieving, by the memory device, a first multiplication result from the memory device using the first floating point input value;
sending, by the memory device, the first multiplication result to a buffer on the logic device;
sending, by the buffer, the first multiplication result to an accumulator on the logic device; and
storing, by the accumulator, the first multiplication result.
3 . The method of claim 1 , wherein the first operation comprises:
using, by the memory device, the second floating point input value to retrieve a second multiplication result from the memory device;
sending, by the memory device, the second multiplication result to a buffer on the logic device;
sending, by the buffer, the second multiplication result to an adjustor on the logic device;
sending, by the adjustor, the second multiplication result to an accumulator on the logic device; and
storing, by the accumulator, the second multiplication result.
4 . The method of claim 1 , wherein the first operation comprises:
retrieving, by the memory device, a tensor multiplication result from the memory device using the first floating point input value;
sending, by the memory device, the tensor multiplication result to a buffer on the logic device; and
sending, by the buffer, the tensor multiplication result to a tensor post-processor on the logic device,
wherein the first floating point input value comprises a tensor floating point input.
5 . The method of claim 1 , wherein the first operation comprises:
retrieving, by the memory device, a first multiplication result from the memory device using the first floating point input value;
sending, by the memory device, the whole product multiplication results to a buffer device comprising a one or more buffers;
sending, by the buffer device, the whole product multiplication result to a buffer of the logic device; and
sending, by the buffer of the logic device, the whole product multiplication result to a tensor processor on the logic device.
6 . The method of claim 1 , further comprising:
reading locations in an input feature map;
performing a convolution operation with the input feature map with a kernel; and
generating results of a second layer input feature map based on the convolution operation.
7 . The method of claim 1 , wherein the memory device comprises a lookup table (LUT).
8 . A memory lookup mechanism comprising:
a logic device; and
a memory device,
wherein the logic device performs operations comprising:
receiving a result of a first operation from a table stored on the memory device; and
performing a second operation using the result of the first operation stored on the memory device,
wherein the result of the first operation is retrieved using a first floating point input value and a second floating point input value, the first floating point input value and the second floating point input value being used as addresses of the result of the first operation on the memory device.
9 . The memory lookup mechanism of claim 8 , wherein the memory device performs operations comprising:
retrieving a first multiplication result from the memory device using the first floating point input value; and
sending the first multiplication result to a buffer on the logic device.
10 . The memory lookup mechanism of claim 9 , wherein the logic device further comprises an accumulator, the accumulator performing operations comprising:
receiving the first multiplication result from the buffer; and
obtaining the first multiplication result.
11 . The memory lookup mechanism of claim 8 , wherein the memory device performs operations further comprising:
retrieving a second multiplication result from the memory device using the second floating point input value; and
sending the second multiplication result to a buffer on the logic device.
12 . The memory lookup mechanism of claim 11 , wherein the logic device further comprises:
an adjustor, the adjustor receiving the second multiplication result from the buffer; and
an accumulator, the accumulator performing operations comprising:
receiving the second multiplication result from the adjustor; and
storing the second multiplication result.
13 . The memory lookup mechanism of claim 8 , wherein the memory device performs operations further comprising:
retrieving a tensor multiplication result from the memory device using the first floating point input value; and
sending the tensor multiplication result to a buffer on the logic device,
wherein the first floating point input value comprises a tensor floating point input.
14 . The memory lookup mechanism of claim 13 , wherein the logic device further comprises a tensor post-processor receiving the tensor multiplication result from the buffer.
15 . The memory lookup mechanism of claim 8 , wherein the memory device performs operations further comprising:
retrieving a first multiplication result from the memory device using the first floating point input value; and
sending a whole product multiplication result to a buffer.
16 . The memory lookup mechanism of claim 15 , wherein the logic device further comprises a tensor processor, the tensor processor receiving the whole product multiplication result from the buffer.
17 . The memory lookup mechanism of claim 8 , wherein the logic device further comprises an accelerator.
18 . The memory lookup mechanism of claim 8 , wherein the memory device comprises a dynamic random access memory (DRAM) device.
19 . The memory lookup mechanism of claim 8 , wherein the table comprises a lookup table (LUT).