Methods and apparatus to boot from block devices

1 . A device comprising:

a first interface configured to couple to a first memory configured to store an image that includes a set of slices;

a second interface configured to couple to a second memory;

a direct memory access circuit coupled to the first and second interfaces and configured to:

receive a transaction that specifies a read of a slice of the set of slices; and

based on the transaction:

read the slice from the first memory;

perform operations to the slice; and

store the slice in the second memory; and

address remapping circuitry coupled to the direct memory access circuit, the address remapping circuitry configured to:

track transactions between the direct memory access circuit and the second memory; and

assert a signal corresponding to the slice and indicating that the slice is stored in the second memory.

2 . The device of claim 1 , wherein:

the direct memory access circuit is a first direct memory access circuit; and

the device further comprises a second direct memory access circuit coupled to the first and second interfaces and configured to, based on a second slice of the set of slices of the image being read from the first memory and stored in the second memory, cause a third slice of the set of slices to be read from the first memory and stored in the second memory.

3 . The device of claim 1 , further comprising an access scheduler circuit coupled to the direct memory access circuit, the access scheduler circuit is configured to:

determine a priority of the transaction based on initiation of the transaction; and

control access to the first memory based on the priority of the transaction.

4 . The device of claim 3 , wherein the access scheduler circuit is configured to determine that the priority of the transaction is a high priority as a result of determining a processor core initiated the transaction.

5 . The device of claim 3 , wherein the access scheduler circuit is configured to determine the priority of the transaction is a low priority as a result of determining a pre-emptive load operation initiated the transaction.

6 . The device of claim 1 , wherein the address remapping circuitry is configured to:

access the slice in the second memory as a result of receiving the transaction from a processor core to access operations of the slice.

7 . The device of claim 6 , further comprising a third interface configured to couple to the processor core.

8 . The device of claim 7 , further comprising an address decoder coupled to the third interface, the address decoder configured to:

receive the transaction from the processor core to access the slice;

assert an indication gate as a result of receiving an indication from the first interface that the set of slices of the image are stored in the second memory;

access the slice in the second memory as a result of the indication gate indicating the set of slices are stored in the second memory; and

transmit the transaction to the address remapping circuitry as a result of the indication gate indicating that one or more portions of the set of slices are stored in the first memory.

9 . The device of claim 1 , further comprising secure zone circuitry coupled to the direct memory access circuit, the secure zone circuitry to:

store a slice digest table including at least one of a slice number, slice pointer, or authentication information for slices comprising the set of slices;

decompress the slice using decompression engine circuitry; and

authenticate the slice based on a comparison of a digital signature of the slice to a verified digital signature stored in the slice.

10 . The device of claim 1 , wherein the operations of the direct memory access circuit includes at least one of authentication or decompression.

11 . The device of claim 1 , wherein the operations of the direct memory access circuit are performed on-the-fly.