Asynchronous finite state machine circuit
An asynchronous finite state machine circuit comprising state circuitry configured to be in one of a plurality of states, and transition between states, wherein the asynchronous finite state machine is configured to detect that a current state is stable before the state circuitry can transition to a next state.
1 . An asynchronous finite state machine circuit comprising:
state circuitry configured to:
i) be in one of a plurality of states; and
ii) transition between the plurality of states; and
a control circuit configured to:
detect that a current state of the state circuitry is stable before the state circuitry can transition to a next state; and
trigger the transition of the state circuitry to the next state upon detection that the current state of the state circuitry is stable such that state transitions are controlled by completion detection.
2 . The asynchronous finite state machine circuit of claim 1 , wherein the state circuitry is configured to provide one or more output signals that are dependent on a state of the state circuitry.
3 . The asynchronous finite state machine circuit of claim 1 , wherein:
the state circuitry comprises one or more state bits; and
each of the one or more state bits is configured to be in one of a plurality of bit states, a state of the state circuitry being dependent on the bit states of the one or more state bits.
4 . The asynchronous finite state machine circuit of claim 1 , wherein:
the state circuitry is configured to provide one or more state indicators to the control circuit; and
the control circuit is configured to detect that the current state of the state circuitry is stable using the one or more state indicators.
5 . The asynchronous finite state machine circuit of claim 4 comprising one or more dual rails, each of the one or more state indicators being provided to the control circuit using a dual rail.
6 . The asynchronous finite state machine circuit of claim 4 , wherein each of the one or more state indicators is configured to have a first value, a second value or a stability value.
7 . The asynchronous finite state machine circuit of claim 6 , wherein at least one of the one or more state indicators having the stability value is indicative of the state circuitry being stable.
8 . The asynchronous finite state machine circuit of claim 6 , wherein all of the of the one or more state indicators having the stability value is indicative of the state circuitry being stable.
9 . The asynchronous finite state machine circuit of claim 6 wherein:
each of the one or more state indicators comprises a first indicator signal and a second indicator signal; and
the value of the state indicator is dependent on the first and second indicator signals.
10 . The asynchronous finite state machine circuit of claim 9 , wherein each of the one or more state indicators has:
the first value when the first indicator signal is one and the second indicator signal is zero;
the second value when the first indicator signal is zero and the second indicator signal is one; and
the stability value when the second indicator signals are both zero.
11 . The asynchronous finite state machine circuit of claim 1 , wherein the control circuit comprises a state update circuit configured to trigger the transition of the state circuitry to the next state.
12 . The asynchronous finite state machine circuit of claim 11 , wherein the state update circuit is quasi delay insensitive.
13 . The asynchronous finite state machine circuit of claim 11 , wherein the control circuit is configured to provide one or more state update signals to the state circuitry to trigger the transition of the state circuitry to the next state.
14 . The asynchronous finite state machine circuit of claim 13 comprising one or more dual rails, each of the one or more state update signals being provided to the state circuitry using a dual rail.
15 . The asynchronous finite state machine circuit of claim 13 , wherein each of the one or more state update signals is configured to have a first value, a second value or a stability value.
16 . The asynchronous finite state machine circuit of claim 15 , wherein:
each of the one or more state update signals comprises a set signal and a reset signal; and
the value of the state update signal is dependent on the set signal and the reset signal.
17 . The asynchronous finite state machine circuit of claim 16 , wherein the one or more state update signals has:
the first value when the set signal is one and the reset signal is zero;
the second value when the set signal is zero and the reset signal is one; and
the stability value when the set signal and the reset signal are both zero.
18 . The asynchronous finite state machine circuit of claim 13 , wherein each of the one or more state update signals is configured to provide a stability value to the state circuitry after a first value or a second value has been provided to the state circuitry.
19 . The asynchronous finite state machine circuit of claim 11 ,
wherein the control circuit comprises a selection circuit configured to:
detect that the current state of the state circuitry is stable; and
provide one or more trigger signals,
wherein the state update circuit is configured to trigger the transition of the state circuitry to the next state based on the one or more trigger signals.
20 . The asynchronous finite state machine circuit of claim 19 ,
wherein the control circuit comprises a sanitization circuit configured to:
receive one or more input signals;
receive the one or more trigger signals; and
provide one or more sanitized signals to the state update circuit, the one or more sanitized signals being dependent on the one or more input signals and the one or more trigger signals, and
wherein:
the one or more sanitized signals are persistent signals.
21 . The asynchronous finite state machine circuit of claim 20 , wherein the one or more trigger signals and/or the one or more sanitized signals comprise three bits that comprise one or fewer bits having a value of one.
22 . A controller for a switching converter, the controller comprising an asynchronous finite state machine circuit comprising:
state circuitry configured to:
i) be in one of a plurality of states; and
ii) transition between the plurality of states; and
a control circuit configured to:
detect that a current state of the state circuitry is stable before the state circuitry can transition to a next state; and
trigger the transition of the state circuitry to the next state upon detection that the current state of the state circuitry is stable such that state transitions are controlled by completion detection.
23 . The controller of claim 22 , wherein:
the switching converter comprises one or more power switches; and
the state circuitry is configured to provide one or more output signals that are dependent on the state of the state circuitry, the one or more output signals being configured to drive a switching operation of the one or more power switches.
24 . A method of operating an asynchronous finite state machine circuit comprising state circuitry configured to be in one of a plurality of states and to transition between the plurality of states, the method comprising:
detecting, using a control circuit of the asynchronous finite state machine, that a current state of the state circuitry is stable; and
triggering, by the control circuit, the transition of the state circuitry to a next state upon detection that the current state of the state circuitry is stable, such that state transitions are controlled by completion detection.