Mapping virtual processor cores to heterogeneous physical processor cores
Mapping virtual processor cores to heterogeneous physical processor cores. A device determines that a processor system has a heterogeneous set of processor cores, which include a first physical core with a first attribute and a second physical core with a second capability different from the first capability. The device associates a plurality of physical cores with a virtual machine (VM). This includes the device associating the first physical core with a first virtual core, which includes, based on the first physical core having the first capability, exposing to the VM that the first virtual core has a first feature set. This also includes the device associating the second physical core with a second virtual core of the VM, which includes, based on the second physical core having the second capability, exposing to the VM that the second virtual core has a second feature set different from the first feature set.
1 . A method, implemented at a computer system that includes a processor system, comprising:
determining that the processor system has a heterogeneous set of physical processor cores, the heterogeneous set of physical processor cores including,
a first physical processor core with a first instruction set architecture (ISA) having a first set of available processor instructions, and
a second physical processor core with a second ISA having a second set of available processor instructions that includes at least one processor instruction not present in the first set of available processor instructions;
associating a plurality of physical processor cores with a virtual machine (VM), including:
associating the first physical processor core with a first virtual processor core of the VM, including, based on the first physical processor core having the first ISA, exposing to the VM that the first virtual processor core has a first feature set; and
associating the second physical processor core with a second virtual processor core of the VM, including, based on the second physical processor core having the second ISA, exposing to the VM that the second virtual processor core has a second feature set different from the first feature set; and
determining, prior to migrating the VM to a target computer system, that the target computer system comprises a target processor system supporting both the first ISA and the second ISA.
2 . The method of claim 1 , wherein,
the first physical processor core has a first performance capability; and
the second physical processor core has is a second performance capability different from the first performance capability.
3 . The method of claim 2 , wherein,
the first performance capability is at least one of a first available clock rate, a first cache size, a first number of arithmetic logic units (ALUs), or a first pipeline architecture; and
the second performance capability is at least one of a second available clock rate different from the first available clock rate, a second cache size different from the first cache size, a second number of ALUs different from the first number of ALUs, or a second pipeline architecture different from the first pipeline architecture.
4 . The method of claim 2 , wherein,
the first feature set indicates an efficiency core; and
the second feature set indicates a performance core.
5 . The method of claim 1 , wherein,
exposing to the VM that the first virtual processor core has the first feature set comprises associating a first central processing unit identifier (CPUID) with the first virtual processor core; and
exposing to the VM that the second virtual processor core has the second feature set comprises associating a second CPUID with the second virtual processor core, the second CPUID being different from the first CPUID.
6 . The method of claim 1 , wherein,
exposing to the VM that the first virtual processor core has the first feature set comprises presenting a first advanced configuration and power interface (ACPI) table entry to the VM; and
exposing to the VM that the second virtual processor core has the second feature set comprises presenting a second ACPI table entry to the VM, the second ACPI table entry being different from the first ACPI table entry.
7 . The method of claim 1 , wherein the method is implemented by a scheduler of a host operating system.
8 . The method of claim 1 , wherein the method is implemented by a hypervisor.
9 . A computer system comprising:
a processor system that comprises a heterogeneous set of physical processor cores, the heterogeneous set of physical processor cores including,
a first physical processor core with a first instruction set architecture (ISA) having a first set of available processor instructions, and
a second physical processor core with a second ISA having a second set of available processor instructions that includes at least one processor instruction not present in the first set of available processor instructions; and
a computer storage medium that stores computer-executable instructions that are executable by the processor system to at least:
associate the first physical processor core with a first virtual processor core of a virtual machine (VM), including, based on the first physical processor core having the first ISA, exposing to the VM that the first virtual processor core has a first feature set;
associate the second physical processor core with a second virtual processor core of the VM, including, based on the second physical processor core having the second ISA, exposing to the VM that the second virtual processor core has a second feature set different from the first feature set; and
determine, prior to migrating the VM to a target computer system, that the target computer system comprises a target processor system supporting both the first ISA and the second ISA.
10 . The computer system of claim 9 , wherein,
the first physical processor core has a first performance capability; and
the second physical processor core has is a second performance capability different from the first performance capability.
11 . The computer system of claim 10 , wherein,
the first performance capability is at least one of a first available clock rate, a first cache size, a first number of arithmetic logic units (ALUs), or a first pipeline architecture; and
the second performance capability is at least one of a second available clock rate different from the first available clock rate, a second cache size different from the first cache size, a second number of ALUs different from the first number of ALUs, or a second pipeline architecture different from the first pipeline architecture.
12 . The computer system of claim 10 , wherein,
the first feature set indicates an efficiency core; and
the second feature set indicates a performance core.
13 . The computer system of claim 9 , wherein,
exposing to the VM that the first virtual processor core has the first feature set comprises associating a first central processing unit identifier (CPUID) with the first virtual processor core; and
exposing to the VM that the second virtual processor core has the second feature set comprises associating a second CPUID with the second virtual processor core, the second CPUID being different from the first CPUID.
14 . The computer system of claim 9 , wherein,
exposing to the VM that the first virtual processor core has the first feature set comprises presenting a first advanced configuration and power interface (ACPI) table entry to the VM; and
exposing to the VM that the second virtual processor core has the second feature set comprises presenting a second ACPI table entry to the VM, the second ACPI table entry being different from the first ACPI table entry.
15 . The computer system of claim 9 , wherein the computer-executable instructions are part of a scheduler of a host operating system, or a hypervisor.
16 . A computer program product comprising a computer storage medium that stores computer-executable instructions that are executable by a processor system to at least:
identify a first physical processor core of the processor system that has a first instruction set architecture (ISA) having a first set of available processor instructions;
associate the first physical processor core with a first virtual processor core of a virtual machine (VM), including, based on the first physical processor core having the first ISA, exposing to the VM that the first virtual processor core has a first feature set;
identify a second physical processor core of the processor system that has a second ISA having a second set of available processor instructions that includes at least one processor instruction not present in the first set of available processor instructions;
associate the second physical processor core with a second virtual processor core of the VM, including, based on the second physical processor core having the second ISA, exposing to the VM that the second virtual processor core has a second feature set different from the first feature set; and
determine, prior to migrating the VM to a target computer system, that the target computer system comprises a target processor system supporting both the first ISA and the second ISA.
17 . The computer program product of claim 16 , wherein,
the first physical processor core has a first performance capability; and
the second physical processor core has a second performance capability different from the first performance capability.
18 . The computer program product of claim 17 , wherein,
the first performance capability is at least one of a first available clock rate, a first cache size, a first number of arithmetic logic units (ALUs), or a first pipeline architecture; and
the second performance capability is at least one of a second available clock rate different from the first available clock rate, a second cache size different from the first cache size, a second number of ALUs different from the first number of ALUs, or a second pipeline architecture different from the first pipeline architecture.
19 . The computer program product of claim 17 , wherein,
the first feature set indicates an efficiency core; and
the second feature set indicates a performance core.
20 . The computer program product of claim 16 , wherein,
exposing to the VM that the first virtual processor core has the first feature set comprises associating a first central processing unit identifier (CPUID) with the first virtual processor core; and
exposing to the VM that the second virtual processor core has the second feature set comprises associating a second CPUID with the second virtual processor core, the second CPUID being different from the first CPUID.