Preserving pattern checking for data integrity across a single wider link and multiple narrower links
A method for checking integrity of data propagated, in either direction, between a first data link having a first data width and a first data speed, and a plurality of second data links each of which has a second data width narrower than the first width and a second data speed slower than the first speed, includes propagating data with a known pattern (a) from the first link to the plurality of second links, or (b) from the plurality of second links to the first link, selecting bits when transitioning (a) from the first link to each link in the plurality of second links, or (b) from each link in the plurality of second links to the first link, in a manner that preserves the known pattern, and checking for the known pattern when receiving the propagated data at (a) the plurality of second links, or (b) the first link.
1 . A method for checking integrity of data propagated, in either direction, between a first data link having a first data width and a first data speed, and a plurality of second data links each of which has a second data width narrower than the first data width and a second data speed slower than the first data speed, the method comprising:
transferring bits of data with a known pattern (a) from the first data link to each link in the plurality of second data links, or (b) from each link in the plurality of second data links to the first data link, the transferring of the bits from the first data link to each link in the plurality of second data links comprises distributing the bits one bit at a time and in a round-robin fashion from the first data link to the plurality of second data links, and the transferring of the bits from each link in the plurality of second data links to the first data link comprises transferring the bits one bit at a time and in a round-robin fashion from the plurality of second data links to the first data link; and
checking the integrity of the data by checking for the known pattern when receiving the data at (a) the plurality of second data links, or (b) the first data link.
2 . The method according to claim 1 , wherein:
the first data link is coupled to a transceiver in an integrated circuit package
the plurality of second data links extend from the transceiver to a respective chiplet in the integrated circuit package; and
checking for the known pattern when receiving the data at the plurality of second data links comprises checking for the known pattern on at least one of the second data links.
3 . The method according to claim 1 , wherein transferring the bits of data with the known pattern comprises propagating a pseudo-random bit sequence (PRBS) pattern of a known order.
4 . The method according to claim 3 , wherein distributing the bits one bit at a time and in a round-robin fashion comprises iteratively transferring i) a current one of the bits to one of the plurality of second data links, and ii) a next one of the bits to a next one of the plurality of second data links, in an order in which the bits are round-robin distributed to the plurality of second data links.
5 . The method according to claim 4 :
the plurality of second data links comprise N data links;
a total of N×M bits are in the PRBS pattern, where M is a number of groups of bits being transferred; and
distributing the bits from the first data link to each of the plurality of second data links comprises
distributing bits in a first group of N bits [N−1:0] of the first data link respectively to bit0 positions of the plurality of the second data links in round-robin fashion,
distributing bits in a second group of N bits [2N−1:N] of the first data link respectively to bit1 positions of the plurality of the second data links in round-robin fashion,
distributing bits in a third group of N bits [3N−1:2N] of the first data link respectively to bit2 positions of the plurality of the second data links in round-robin fashion, and
continuing to distribute M−3 remaining groups of N bits until bits in an Mth group of N bits [(M×N)1:(M−1)×N] of the first data link has been distributed respectively to bit(M−1) positions of the plurality of second data links in round-robin fashion.
6 . The method according to claim 3 , wherein transferring the bits from the plurality of second data links to the first data link comprises transferring a bit from a corresponding position in each respective link in the plurality of second data links to the first data link.
7 . The method according to claim 6 , wherein the plurality of second data links comprises a number of second data links that is a power of 2.
8 . The method according to claim 7 , wherein the known order of the PRBS pattern on each respective data link in the plurality of second data links is identical to a known order of a PRBS pattern on each other data link in the plurality of second data links.
9 . The method according to claim 8 , wherein, when transferring the bits from the plurality of second data links to the first data link, a number of intervals between initial seeds of the PRBS patterns on each respective data link in the plurality of second data links is a function of i) the known order of the PRBS pattern, and ii) the number of second data links in the plurality of second data links.
10 . The method according to claim 6 , wherein:
the plurality of second data links comprises N second data links;
the known pattern is a PRBS pattern that includes N×M bits, where M is a number of groups of bits being transferred; and
transferring the bits one bit at a time and in a round-robin fashion comprises:
transferring a bit in a bit0 position of each one of the N second data links, in round-robin fashion, to the first data link to form a first group of N bits [N−1:0] on the first data link,
transferring a bit in a bit1 position of each one of the N second data links, in round-robin fashion, to the first data link to form a second group of N bits [2N−1:N] on the first data link,
transferring a bit in a bit2 position of each one of the N second data links, in round-robin fashion, to the first data link to form a third group of N bits [3N−1:2N] on the first data link, and
continuing to transfer bits in M−3 remaining bit(M−1) positions of each one of the N second data links, in round-robin fashion, to the first data link to form an Mth group of N bits [(M×N)−1:(M−1)×N] on the first data link.
11 . An apparatus for checking integrity of data propagated, in either direction, between a first data link having a first data width and a first data speed, and a plurality of second data links each of which has a second data width narrower than the first data width and a second data speed slower than the first data speed, the apparatus comprising:
data mapping circuitry configured to transfer bits of data having a known pattern (a) from the first data link to each link in the plurality of second data links, or (b) from each link in the plurality of second data links to the first data link, the transferring of the bits from the first data link to each link in the plurality of second data links comprises distributing the bits one bit at a time and in a round-robin fashion from the first data link to the plurality of second data links, and the transferring of the bits from each link in the plurality of second data links to the first data link comprises transferring the bits one bit at a time and in a round-robin fashion from the plurality of second data links to the first data link; and
circuitry configured to check the integrity of the data by checking for the known pattern when receiving the data at (a) the plurality of second data links, or (b) the first data link.
12 . The apparatus according to claim 11 , wherein the circuitry comprises a single instance of pattern-checking circuitry for all of the apparatus.
13 . The apparatus according to claim 11 , wherein the circuitry comprises multiple instances of identical pattern-checking circuitry throughout the apparatus.
14 . The apparatus according to claim 11 , wherein, the circuitry is configured i) to check for the known pattern when receiving the bits of data at the plurality of second data links, and ii) to check for the known pattern on a portion of one of the plurality of second data links between a first device and a second device, the first device being connected between the first data link and the second data link.
15 . The apparatus according to claim 11 , wherein the bits have a pseudo-random bit sequence (PRBS) pattern of a known order.
16 . The apparatus according to claim 11 , wherein the data mapping circuitry configured, when distributing the bits one bit at a time and in a round-robin fashion, to iteratively transfer i) a current one of the bits to one of the plurality of second data links, and ii) a next one of the bit to a next one of the plurality of second data links, in an order in which the bits are round-robin distributed to the plurality of second data links.
17 . The apparatus according to claim 15 , wherein:
the plurality of second data links comprise N data links;
a total of N×M bits are in the PRBS pattern, where M is a number of groups of bits being transferred; and
the data mapping circuitry is configured, when distributing the bits from the first data link to each of the plurality of second data links, to
distribute bits in a first group of N bits [N−1:0] of the first data link respectively to bit0 positions of the plurality of the second data links in round-robin fashion;
distribute bits in a second group of N bits [2N−1:N] of the first data link to respectively bit1 positions of the plurality of the second data links in round-robin fashion;
distribute bits in a third group of N bits [3N−1:2N] of the first data link respectively to bit2 positions of the plurality of the second data links in round-robin fashion; and
continue to distribute M−3 remaining groups of N bits until each bit in an Mth group of N bits [(M×N)1:(M−1)×N] of the first data link has been distributed respectively to bit(M−1) positions of the plurality of the second data links in round-robin fashion.
18 . The apparatus according to claim 15 , wherein the data mapping circuitry is configured, when transferring the bits from the plurality of second data links to the first data link, to transfer a bit from a corresponding position in each respective link in the plurality of second data links to the first data link.
19 . The apparatus according to claim 18 , wherein the plurality of second data links comprises a number of second data links that is a power of 2.
20 . The apparatus according to claim 19 , wherein the known order of the PRBS pattern is identical to a known order of a PRBS pattern propagated on each other data link in the plurality of second data links.
21 . The apparatus according to claim 20 , wherein the circuitry is configured, when transferring the bits from the plurality of second data links to the first data link, is distribute the bits such that a number of intervals between initial seeds of the PRBS patterns on each respective data link in the plurality of second data links is a function of i) the known order of the PRBS pattern, and ii) the number of second data links in the plurality of second data links.
22 . The apparatus according to claim 18 , wherein:
the plurality of second data links comprises N data links;
the known pattern is a PRBS pattern that includes a total of N×M bits, where M is a number of groups of bits being transferred; and
the data mapping circuitry is configured, when transferring the bits from the plurality of second data links to the first data link, to
coalesce a bit in a bit0 position of each one of the N second data links, in round-robin fashion, to the first data link to form a first group of N bits [N−1:0] on the first data link,
coalesce a bit in a bit1 position of each one of the N second data links, in round-robin fashion, to the first data link to form a second group of N bits [2N−1:N] on the first data link,
coalesce a bit in a bit2 position of each one of the N second data links, in round-robin fashion, to the first data link to form a third group of N bits [3N−1:2N] on the first data link, and
continue to coalesce bits in M−3 remaining bit(M−1) positions of each one of the N second data links, in round-robin fashion, to the first data link to form an Mth group of N bits [(M×N)1:(M−1)×N] on the first data link.