Decoding method and decoder device used in flash memory controller capable of reducing design complexity and circuit costs

1 . A decoder device used in a flash memory controller, the flash memory controller being used to be coupled between a host device and a flash memory, and the decoder device comprises:

a syndrome calculation check circuit, for calculating a syndrome value of a variable node V i of a parity check matrix according to a plurality of bits of a received input data, the parity check matrix including N×M sub-matrices formed by multiple variable nodes V 1 −V N and multiple check nodes C 1 −C M , a value of i being in 1−N;

a first barrel shifter, coupled to the syndrome calculation check circuit, for rotating the syndrome value of the variable node V i into a vertical direction of a variable node V i+1 to generate an estimated syndrome value of the variable node V i+1 ;

a second barrel shifter, coupled to the syndrome calculation check circuit, for rotating a syndrome value of a variable node V i−1 into a vertical direction of a variable node V i+Δ to generate information of a rotated syndrome value;

a variable weighted-sum calculation circuit, coupled to the second barrel shifter, for determining a plurality of weight values based on information of a plurality of rotated syndrome values outputted by the second barrel shifter to perform a weighted-sum calculation upon the information of the plurality of rotated syndrome values to generate a flipping function value; and

a flipping circuit, coupled to the variable weighted-sum calculation circuit, for comparing the flipping function value with a flipping threshold value to generate a flipping result;

wherein the syndrome calculation check circuit determines whether to flip a specific bit of the plurality of bits according to the flipping result; when determining to flip the specific bit, the syndrome calculation check circuit calculates a syndrome value of the variable node V i+1 based on the flipped specific bit; and, when determining not to flip the specific bit, the syndrome calculation check circuit uses the estimated syndrome value of the variable node V i+1 generated by the first barrel shifter as the syndrome value of the variable node V i+1 .

2 . The decoder device of claim 1 , wherein both the first barrel shifter and the second barrel shifter operate in a variable node domain, and neither the first barrel shifter nor the second barrel shifter performs a rotation operation from the variable node domain into a check node domain.

3 . The decoder device of claim 1 , wherein a value of Δ is equal to a number of maximum delay stages of circuit units included in the decoder device.

4 . The decoder device of claim 3 , wherein the value of Δ is equal to four.

5 . The decoder device of claim 1 , wherein the first barrel shifter and the second barrel shifter operate in parallel, and the first barrel shifter is located in a circuit loop which is different from a circuit loop in which the second barrel shifter is located.

6 . A decoding method of a decoder device used in a flash memory controller, the flash memory controller being used to be coupled between a host device and a flash memory, and the decoding method comprises:

using a syndrome calculation check circuit to calculate a syndrome value of a variable node V i of a parity check matrix according to a plurality of bits of a received input data, the parity check matrix including N×M sub-matrices formed by multiple variable nodes V 1 −V N and multiple check nodes C 1 −C M , a value of i being in 1−N;

using a first barrel shifter to rotate the syndrome value of the variable node V i into a vertical direction of a variable node V i+1 to generate an estimated syndrome value of the variable node V i+1 ;

using a second barrel shifter to rotate a syndrome value of a variable node V i−1 into a vertical direction of a variable node V i+Δ to generate information of a rotated syndrome value;

using a variable weighted-sum calculation circuit to determine a plurality of weight values based on information of a plurality of rotated syndrome values outputted by the second barrel shifter to perform a weighted-sum calculation upon the information of the plurality of rotated syndrome values to generate a flipping function value;

comparing the flipping function value with a flipping threshold value to generate a flipping result;

using the syndrome calculation check circuit to determine whether to flip a specific bit of the plurality of bits according to the flipping result;

when determining to flip the specific bit, using the syndrome calculation check circuit to calculate a syndrome value of the variable node V i+1 based on the flipped specific bit; and

when determining not to flip the specific bit, using the syndrome calculation check circuit to use the estimated syndrome value of the variable node V i+1 generated by the first barrel shifter as the syndrome value of the variable node V i+1 .

7 . The decoding method of claim 6 , wherein both the first barrel shifter and the second barrel shifter operate in a variable node domain, and neither the first barrel shifter nor the second barrel shifter performs a rotation operation from the variable node domain into a check node domain.

8 . The decoding method of claim 6 , wherein a value of Δ is equal to a number of maximum delay stages of circuit units included in the decoder device.

9 . The decoding method of claim 8 , wherein the value of Δ is equal to four.

10 . The decoding method of claim 6 , wherein the first barrel shifter and the second barrel shifter operate in parallel, and the first barrel shifter is located in a circuit loop which is different from a circuit loop in which the second barrel shifter is located.