Reliability availability serviceability (RAS) service framework
Examples described herein relate to execution of multiple Reliability Availability Serviceability (RAS) processes on different processors of the at least two processors to provide fallback from a first RAS process to a second RAS process executing on a processor of the at least two processors based on failure or timeout of the first RAS process. In some examples, the different processors comprise independently operating processors whereby failure or inoperability of one of the different processors is independent of another of the different processors. In some examples, failure or timeout of the first RAS process comprises failure of the second RAS process to receive an operating status signal from the first RAS process.
1 . At least one non-transitory computer-readable medium, comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
execute multiple Reliability Availability Serviceability (RAS) processes on different processors of the two or more processors to provide fallback from a first RAS process to a second RAS process executing on a processor of the one or more processors based on failure or timeout of the first RAS process, wherein the first RAS process performs a corrective action in response to an indication of a memory or device interface error and wherein the first RAS process and the second RAS process comprise at least one finite-state machine (FSM) including one or more atomic transaction state blocks.
2 . The computer-readable medium of claim 1 , wherein the different processors comprise independently operating processors whereby failure or inoperability of one of the different processors is independent of another of the different processors.
3 . The computer-readable medium of claim 1 , wherein failure or timeout of the first RAS process comprises:
failure of the second RAS process to receive an operating status signal from the first RAS process.
4 . The computer-readable medium of claim 3 , wherein the second RAS process is to receive an operating status signal from the first RAS process by reading a register or memory region and wherein the operating status signal indicates whether the first RAS process is operational.
5 . The computer-readable medium of claim 1 , wherein the fallback from the first RAS process to the second RAS process executing on a processor of the one or more processors comprises the second RAS process accessing a RAS event uncompleted by the first RAS process.
6 . The computer-readable medium of claim 1 , wherein the corrective action performs one or more of: correctable memory error handling, uncorrectable memory error handling, or handling a device interface error.
7 . The computer-readable medium of claim 1 , wherein failure or timeout of the first RAS process comprises:
failure of the first RAS process to complete processing a RAS message within a configured amount of time.
8 . An apparatus comprising:
at least two processors to execute multiple Reliability Availability Serviceability (RAS) processes on different processors of the at least two processors to provide fallback from a first RAS process to a second RAS process executing on a processor of the at least two processors based on failure or timeout of the first RAS process, wherein the first RAS process is to perform a corrective action in response to an indication of a memory or device interface error and wherein the first RAS process and the second RAS process comprise at least one finite-state machine (FSM) including one or more atomic transaction state blocks.
9 . The apparatus of claim 8 , wherein the different processors comprise independently operating processors whereby failure or inoperability of one of the different processors is independent of another of the different processors.
10 . The apparatus of claim 8 , wherein failure or timeout of the first RAS process comprises:
failure of the second RAS process to receive an operating status signal from the first RAS process.
11 . The apparatus of claim 10 , wherein the second RAS process is to receive an operating status signal from the first RAS process by reading a register or memory region.
12 . The apparatus of claim 8 , wherein the fallback from a first RAS process to a second RAS process executing on a processor of the at least two processors comprises the second RAS process accessing a RAS event uncompleted by the first RAS process.
13 . The apparatus of claim 12 , wherein the RAS event comprises one or more of:
correctable memory error handling, uncorrectable memory error handling, or device interface error.
14 . A method comprising:
executing multiple Reliability Availability Serviceability (RAS) processes on different processors to provide fallback from a first RAS process to a second RAS process executing on a processor based on failure or timeout of the first RAS process, wherein the first RAS process performs a corrective action in response to an indication of a memory or device interface error and wherein the first RAS process and the second RAS process comprise at least one finite-state machine (FSM) including one or more atomic transaction state blocks.
15 . The method of claim 14 , wherein the different processors are in different processor partitions.
16 . The method of claim 14 , wherein the second RAS process is to receive an operating status signal from the first RAS process by reading a register or memory region.
17 . The method of claim 14 , wherein the first and second processes are to handle RAS events and wherein RAS events comprise one or more of: correctable memory error handling, uncorrectable memory error handling, or device interface error.