IP Library Granted Patent US 12664064
Granted Patent B2
US 12664064 · App. 18/671,705 · Granted Jun 23, 2026

Systems and methods for handling communications between a host Operating System (OS) application and a display controller through an Embedded Controller (EC)

Inventors: Ibrahim Sayyed (Georgetown, TX); Adolfo S. Montero (Pflugerville, TX); Shane L. Yarbrough (Tuscola, TX)
Assignee: Dell Products L.P.
G06F11/27
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Quick Facts
Patent No.
US 12664064
App. No.
18/671,705
Granted
Jun 23, 2026
Kind
B2
Abstract

Systems and methods for handling communications between a host Operating System (OS) application and a display controller through an Embedded Controller (EC) are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive, by a kernel driver of a host OS, a message from a host OS application; and at least in part in response to a determination that the processor comprises a Reduced Instruction Set Computer (RISC) processor, send a request to an EC, where the request is configured to cause the EC to trigger a display's Built-In Self-Test (BIST) by a display controller.

Claims (28)

1 . An Information Handling System (IHS), comprising:

a processor; and

a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to:

receive, by a kernel driver of a host Operating System (OS), a message from a host OS application;

at least in part in response to a determination that the processor comprises a Reduced Instruction Set Computer (RISC) processor, send a request to an Embedded Controller (EC), wherein the request is configured to cause the EC to trigger a display's Built-In Self-Test (BIST) by a display controller, wherein the EC triggers the BIST without the IHS entering a System Management Mode (SMM), without any reboot, and without any reset; and

at least in part in response to a determination that the processor comprises a Complex Instruction Set Computer (CISC) processor, abstain from sending the message to the EC and notify a user of the IHS that the BIST cannot be triggered by the host OS at runtime.

2 . The IHS of claim 1 , wherein the EC is configured to use hardware-based security architecture registers accessible via a hardware-based security architecture driver.

3 . The IHS of claim 2 , wherein the hardware-based security architecture driver comprises a TRUSTZONE driver.

4 . The IHS of claim 1 , wherein the message is received, at least in part, in response to a result of a diagnostic operation of a display driver associated with the display controller.

5 . The IHS of claim 1 , wherein the host OS application is configured to trigger a diagnostic operation of a display driver associated with the display controller, at least in part, concurrently with the display's BIST.

6 . The IHS of claim 1 , wherein the EC is configured to trigger the BIST without the IHS entering a System Management Mode (SMM).

7 . The IHS of claim 1 , wherein at least in part in response to the determination that the processor comprises the RISC processor, the program instructions, upon execution, further cause the EC to send the request to the display controller at runtime, without reboot, and without reset.

8 . The IHS of claim 1 , wherein at least in part in response to the determination that the processor comprises the CISC processor, the program instructions, upon execution, further cause the IHS to inform a user of the IHS that the display's BIST cannot be executed at runtime, without reboot, or without reset.

9 . An Information Handling System (IHS), comprising:

a processor; and

a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to:

receive, by a kernel driver of a host Operating System (OS), a message from a host OS application; and

at least in part in response to a determination that the processor comprises a Reduced Instruction Set Computer (RISC) processor, send a request to an Embedded Controller (EC), wherein the request is configured to cause the EC to trigger a display's Built-In Self-Test (BIST) by a display controller, and wherein the EC may be configured to trigger the BIST without the IHS entering a System Management Mode (SMM), without any reboot, and without any reset;

wherein the message comprises a first Application Programming Interface (API) call, wherein the request comprises a second API call, and wherein the program instructions, upon execution, further cause the kernel driver to translate the first API call into the second API call based, at least in part, upon a Look-Up-Table (LUT).

10 . The IHS of claim 9 , wherein the kernel driver is configured to translate the first API call into the second API call based, at least in part, upon a policy.

11 . The IHS of claim 10 , wherein the policy comprises one or more rules usable to translate the message based, at least in part, upon an entitlement verification.

12 . The IHS of claim 10 , wherein the policy comprises one or more rules usable to translate the message based, at least in part, upon context information.

13 . The IHS of claim 12 , wherein the context information comprises at least one of: a location of the IHS, an identity of a user of the IHS, a host Operating System (OS) of the IHS, an identity of the host OS application, or a network connectivity of the IHS.

14 . In an Information Handling System (IHS), a method comprising:

receiving, by an Embedded Controller (EC), a message from a kernel driver, wherein the message comprises a request originated by a host Operating System (OS) application executed by a processor to cause the EC to trigger a display's Built-In Self-Test (BIST), wherein the request comprises a first Application Programming Interface (API) call, wherein the kernel driver is configured to send a translated request to the EC, and wherein the translated request comprises a second API call, and wherein the EC may be configured to trigger the BIST without the IHS entering a System Management Mode (SMM), without any reboot, and without any reset;

translating the first API call into the second API call based, at least in part, upon a Look-Up-Table (LUT); and

providing, by the kernel driver, a response from the EC to the host OS application.

15 . The method of claim 14 , wherein the kernel driver is configured to send the request to the EC at least in part in response to a determination that the processor comprises a Reduced Instruction Set Computer (RISC) processor.