Methods and apparatus for real-time trip sequence detection for cascaded trip events
Systems, apparatus, articles of manufacture, and methods are disclosed for real-time trip sequence detection for cascaded trip events. An example integrated circuit device includes trip detector circuitry, a first counter, a first memory, a second counter, a second memory, and control circuitry in communication with the trip detector circuitry, the control circuitry to, in response to a first trigger detected by the fault detector circuit, store a value of the first counter in the first memory, and in response to a second trigger detected by the fault detector circuit, store a value of the second counter in the second memory. The trip detector circuitry will continue the same detection, identification and counter storage logic for the subsequent triggers limited only by the available storage capacity.
1 . A device comprising:
trip detector circuitry configured to detect trip events including a first trip event and a second trip event;
a first counter configured to store a value representing a time of detection of the first trip event;
a first memory;
a second counter configured to store a value representing a time elapsed between detection of the first trip event and detection of the second trip event;
a second memory; and
control circuitry in communication with the trip detector circuitry and configured to:
in response to the first trip event detected by the trip detector circuitry, store the value of the first counter in the first memory; and
in response to the second trip event detected by the trip detector circuitry, store the value of the second counter in the second memory.
2 . The device of claim 1 , wherein the first memory includes a sixty-four bit field configured to store the value of the first counter.
3 . The device of claim 2 , wherein the first counter is a sixty-four bit counter.
4 . The device of claim 1 , wherein the second counter is a sixty-four bit counter with pre-scale support.
5 . The device of claim 4 , wherein the second memory includes a ninety-six bit field and the control circuitry is configured to store an identifier of a source of the second trip event, in addition to the value of the second counter, in the second memory.
6 . The device of claim 4 , further including a trip identifier register configured to store a trip storage location identifier, wherein the control circuitry is configured to store the value of the second counter at a location in the second memory based on the trip storage location identifier.
7 . The device of claim 6 , wherein the trip detector circuitry is configured to increment the trip storage location identifier in response to detection of at least one of the first trip event or the second trip event.
8 . The device of claim 1 , further including communication circuitry configured to provide the values stored in the first memory and the second memory to a logic circuit separate from the device.
9 . The device of claim 1 , wherein the first trip event is a hardware-based trip event and the second trip event is a software-based trip event.
10 . The device of claim 9 , further including communication circuitry configured to enable logic circuitry external to the device to provide a trigger signal for the software-based trip event.
11 . An apparatus comprising:
a first counter configured to store a first value representing a time of detection of a first trip event;
a second counter configured to store a second value representing a time elapsed between detection of the first trip event and detection of a second trip event;
interface circuitry;
memory configured to store instructions; and
programmable circuitry configured to execute the instructions to:
detect the first trip event via trip detector circuitry;
store the first value of a first counter in a first memory;
detect the second trip event via the trip detector circuitry; and
store the second value of a second counter in a second memory that is distinct from the first memory.
12 . The apparatus of claim 11 , further including the first memory, wherein the first memory is a sixty-four bit memory.
13 . The apparatus of claim 12 , further including the first counter, wherein the first counter is a sixty-four bit counter.
14 . The apparatus of claim 11 , wherein the second memory includes a ninety-six bit register and the programmable circuitry is configured to execute the instructions to store an identifier of a source of the second trip event, in addition to the second value of the second counter, in the second memory.
15 . The apparatus of claim 14 , wherein the programmable circuitry is configured to execute the instructions to store the second value of the second counter at a location in the second memory based on a value of a trip storage location identifier.
16 . The apparatus of claim 15 , wherein the programmable circuitry is configured to execute the instructions to increment the trip storage location identifier in response to detection of at least one of the first trip event or the second trip event.
17 . The apparatus of claim 11 , wherein the interface circuitry is configured to provide the first and second values stored in the first memory and the second memory to a logic circuit separate from the apparatus.
18 . The apparatus of claim 11 , wherein the first trip event is a hardware-based trip event and the second trip event is a software-based trip event.
19 . The apparatus of claim 18 , wherein the interface circuitry is configured to enable logic circuitry separate from the apparatus to provide a trigger signal for the software-based trip event.
20 . A method comprising:
counting, by a first counter, a first value to represent a time elapsed between boot of a system and detection of a first trip of the system by trip detector circuitry;
storing, in response to the detection of the first trip by the trip detector circuitry, the first value of a first counter in a first memory;
counting, by a second counter, a second value to represent a time elapsed between detection of the first trip and detection of a second trip of the system by the trip detector circuitry; and
storing, in response to the detection of the second trip by the trip detector circuitry, the second value of the first counter in a second memory that is distinct from the first memory.
21 . A system comprising:
a first crossbar circuit configured to produce a first signal and second signal;
a data source configured to produce a third signal;
a second crossbar circuit coupled to the first crossbar circuit and to the data source, the second crossbar circuit configured to:
receive the second signal;
receive the third signal; and
produce a fourth signal based on the second signal and the third signal;
pulse width modulation (PWM) modules coupled to the first crossbar circuit and to the second crossbar circuit, wherein the PWM modules are configured to produce PWM signals based on the first signal and the fourth signal; and
trip logger circuitry coupled to the first crossbar circuit and to the data source, the trip logger circuitry configured to:
detect a first trip event and a second trip event based on the second signal or the third signal;
store a value representing a time of detection of the first trip event in a first counter;
store a value representing a time elapsed between detection of the first trip event and detection of the second trip event in a second counter;
in response to detecting the first trip event, store the value of the first counter in a first memory; and
in response to detecting the second trip event, store the value of the second counter in a second memory.