Memory device, CXL memory device, system in package, and system on chip including high bandwidth memory
A compute express link (CXL) memory device may include a high bandwidth memory (HBM) comprising a CXL base die and a plurality of core dies that are sequentially stacked on the CXL base die. The CXL base die may include an HBM interface intellectual property (IP) core configured to convert data transmission and reception between the plurality of core dies and dynamic random access memory (DRAM) in compliance with a CXL specification, and the HBM interface IP core corresponds to a non-Joint Electron Device Engineering Council (JEDEC) standard.
1 . A compute express link (CXL) memory device comprising:
a high bandwidth memory (HBM) comprising a CXL base die and a plurality of core dies that are sequentially stacked on the CXL base die,
wherein the CXL base die comprises
an HBM controller;
a CXL interface circuit;
a bus configured to connect the HBM controller to the CXL interface circuit, and operate based on a double data rate (DDR) PHY interface (DFI) protocol; and
an HBM interface intellectual property (IP) core configured to convert data transmission and reception with dynamic random access memory (DRAM) of the plurality of core dies in compliance with a CXL specification, through a direct conversion of an interface of the HBM interface IP core into the DFI protocol, and
wherein the HBM interface IP core operates regardless of a Joint Electron Device Engineering Council (JEDEC) standard.
2 . The CXL memory device of claim 1 ,
wherein the HBM interface IP core further comprises:
a through silicon via (TSV) input and output (IO) block configured to process an input to and an output from the plurality of core dies; and
a soft macro block configured to perform the direct conversion for complying with the DFI protocol.
3 . The CXL memory device of claim 1 wherein the CXL interface circuit further comprises:
a CXL controller; and
a communication interface block configured to support at least one of peripheral component interconnect express (PCIe) and universal chipset interconnect express (UCIe) communication interfaces.
4 . The CXL memory device of claim 1 , wherein the CXL interface circuit is configured to connect the CXL memory device to an application specific integrated circuit (ASIC) die via an interposer, and
wherein the ASIC die comprises at least one central processing unit (CPU), at least one graphics processing unit (GPU), and at least one neural processing unit (NPU).
5 . The CXL memory device of claim 1 , wherein the CXL base die and the plurality of core dies of the HBM are stacked through a through silicon via (TSV) to form a three-dimensional (3D) memory stack.
6 . The CXL memory device of claim 1 , wherein the CXL base die further comprises:
a test module configured to verify a normal operation of the HBM; and
a boot module configured to perform a booting process of the HBM.
7 . A system-in-package (SiP) comprising:
an application specific integrated circuit (ASIC) die;
a compute express link (CXL) base die, which is vertically connected through a through silicon via (TSV), to a high bandwidth memory (HBM) comprising a plurality of core dies; and
an interposer connecting the ASIC die to the CXL base die,
wherein the CXL base die comprises:
an HBM controller;
a CXL interface circuit;
a bus configured to connect the HBM controller to the CXL interface circuit, and operate based on a double data rate (DDR) PHY interface (DFI) protocol; and
an HBM interface intellectual property (IP) core to convert data transmission and reception with dynamic random access memory (DRAM) of the plurality of core dies in compliance with the data transmission and reception matches a CXL specification, through a direct conversion of an interface of the HBM interface IP core into the DFI protocol, and
wherein the HBM interface IP core operates regardless of a Joint Electron Device Engineering Council (JEDEC) standard.
8 . The SiP of claim 7 ,
wherein the HBM interface IP core further comprises:
wherein a TSV input and output (IO) block configured to process an input to and an output from the plurality of core dies; and
wherein a soft macro block configured to perform the direct conversion for complying with the DFI protocol.
9 . The SiP of claim 7 , wherein the CXL interface circuit further comprises:
a CXL controller; and
a communication interface block configured to support at least one of peripheral component interconnect express (PCIe) and universal chipset interconnect express (UCIe) communication interfaces.
10 . The SiP of claim 7 , wherein the ASIC die comprises at least one central processing unit (CPU), at least one graphics processing unit (GPU), and at least one neural processing unit (NPU).
11 . The SiP of claim 7 , wherein the CXL base die further comprises
a test module configured to verify a normal operation of the HBM; and
a boot module configured to perform a booting process of the HBM.
12 . A memory device comprising
a high bandwidth memory (HBM) comprising a base die and a plurality of core dies that are sequentially stacked on the base die,
wherein the base die comprises:
an HBM controller;
a communication interface circuit;
a bus configured to connect the HBM controller to the communication interface circuit, and operate based on a double data rate (DDR) PHY interface (DFI) protocol; and
an HBM interface intellectual property (IP) core configured to convert data transmission and reception with dynamic random access memory (DRAM) of the plurality of core dies in compliance with peripheral component interconnect express (PCIe), universal chipset interconnect express (UCIe), and die-to-die (D2D) interfaces, through a direct conversion of an interface of the HBM interface IP core into the DFI protocol, and
wherein the HBM interface IP core operates regardless of a Joint Electron Device Engineering Council (JEDEC) standard.
13 . The memory device of claim 12 ,
wherein the HBM interface IP core further comprises:
a through silicon via (TSV) input and output (IO) block configured to process an input to and an output from the plurality of core dies; and
a soft macro block configured to perform the direct conversion for complying with the DFI protocol.
14 . The memory device of claim 12 , wherein the communication interface circuit connects the memory device to an application specific integrated circuit (ASIC) die via an interposer.
15 . The memory device of claim 14 , wherein the ASIC die comprises at least one central processing unit (CPU), at least one graphics processing unit (GPU), and at least one neural processing unit (NPU).
16 . The memory device of claim 12 , wherein the base die and the plurality of core dies of the HBM are stacked through a through silicon via (TSV) to form a three-dimensional (3D) memory stack.
17 . The memory device of claim 12 , wherein the base die further comprises:
a test module configured to verify a normal operation of the HBM; and
a boot module configured to perform a booting process of the HBM.