IP Library Granted Patent US 12664097
Granted Patent B2
US 12664097 · App. 18/786,577 · Granted Jun 23, 2026

Memory module for managing eviction of cache data, memory system including memory module, and method of operating the same

Inventor: Sung Woo Hyun (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
G06F12/0891G06F12/126G06F13/4221
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Quick Facts
Patent No.
US 12664097
App. No.
18/786,577
Granted
Jun 23, 2026
Kind
B2
Abstract

The present technology relates to an electronic device. According to the present technology, a memory system includes a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface and having a tier lower than that of the first memory module. The first memory module comprises a memory device and a memory controller. The memory device may store cache data. The memory controller may store access pattern information of the host for the memory device, select candidate data to be evicted among the cache data based on the access pattern information of the host and a plurality of algorithms, and evict target data among the candidate data.

Claims (19)

1 . A memory system comprising:

a first memory module communicating with a host through a first interface; and

a second memory module communicating with the host through a second interface and having a tier lower than that of the first memory module,

wherein the first memory module comprises:

a memory device configured to store cache data; and

a memory controller configured to store access pattern information of the host for the memory device, select candidate data to be evicted among the cache data based on the access pattern information of the host and a plurality of algorithms, and evict target data among the candidate data, and

wherein the memory controller comprises:

a map management data storage configured to store the access pattern information of the host and an evict table indicating an evict priority of the candidate data; and

an evict controller configured to evict the target data among the candidate data from the memory device by referring to the evict table.

2 . The memory system of claim 1 , wherein the evict controller calculates the evict priority of the candidate data using at least one of the plurality of algorithms including a temporal locality algorithm and a spatial locality algorithm.

3 . The memory system of claim 1 , wherein the first interface includes a dual inline memory module (DIMM) interface, and

the second interface includes a compute express link (CXL) interface.

4 . A method of operating a memory system including a first memory module and a second memory module having a tier lower than that of the first memory module at a request of a host, the method comprising:

selecting candidate data to be evicted among cache data based on access pattern information of the host for the cache data stored in the first memory module and a plurality of algorithms;

generating an evict table indicating an evict priority of the candidate data among the cache data; and

evicting target data among the candidate data based on the evict table.

5 . The method of claim 4 , wherein the plurality of algorithms includes at least one of a temporal locality algorithm, a spatial locality algorithm, a branch locality algorithm, an equidistant locality algorithm, and a sequential locality algorithm.

6 . The method of claim 4 , wherein the first memory module communicates with the host through a dual inline memory module (DIMM) interface, and

the second memory module communicates with the host through a compute express link (CXL) interface.