Storage-side page tables for memory systems
This application is directed to accessing data in a memory system of an electronic system. The memory system a storage-side DRAM and one or more memory channels. The memory system receives a memory access request for target data stored in the memory system, and the memory access request includes a target virtual address of the target data. In response to the memory access request, the memory system searches a page table of the storage-side dynamic random-access memory (DRAM) for a target physical address mapped to the target virtual address of the target data. The page table includes mappings between a plurality of virtual addresses and a plurality of physical addresses of the storage-side DRAM. Based on a search result, the memory system extracts the target data stored in one of the storage-side DRAM and the one or more memory channels according to the target physical address.
1 . A method for accessing data in a memory system, the method comprising:
receiving a memory access request for target data stored in the memory system, wherein the memory access request includes a target virtual address of the target data, and the memory system includes a storage-side dynamic random-access memory (DRAM) and one or more memory channels; and
in response to the memory access request:
searching a page table of the storage-side DRAM for a target physical address mapped to the target virtual address of the target data, wherein the page table includes mappings between a plurality of virtual addresses and a plurality of physical addresses; and
based on a search result, extracting the target data stored in one of the storage-side DRAM and the one or more memory channels according to the target physical address in the page table;
wherein the memory system is coupled to a host device including a translation lookaside buffer (TLB) that stores a plurality of recent translations of virtual addresses to physical addresses, and the host device is configured to, after extracting the target data, store a first recent translation of the target virtual address to the target physical address of the memory system among the plurality of recent translations in the TLB.
2 . The method of claim 1 , wherein the search result includes a page table hit, and extracting the target data further comprises, in accordance with the page table hit:
identifying the target physical address corresponding to the target virtual address in the storage-side DRAM based on the page table; and
extracting the target data that is stored in the storage-side DRAM according to the target physical address.
3 . The method of claim 1 , wherein the search result includes a page table miss, and extracting the target data further comprises, in accordance with the page table miss:
identifying the target physical address corresponding to the target virtual address in the one or more memory channels; and
extracting the target data that is stored in the one or more memory channels according to the target physical address.
4 . The method of claim 3 , wherein the one or more memory channels include one or more of a single-level cell (SLC) memory, a multiple-level cell (MLC) memory, a triple-level cell (TLC) memory, a quad-level cell (QLC) memory, a penta-level memory (PLC), and a higher-level cell memory, and the target physical address of the target data is identified in the one or more memory channels.
5 . The method of claim 3 , wherein the one or more memory channels include at least a first memory in which each memory cell has a first latency and a second memory in which each memory cell has a second latency, the second latency greater than the first latency, extracting the target data further comprising:
determining that the second memory includes the target physical address and is unmapped for the target data; and
in accordance with a determination that the second memory is unmapped in the first memory, moving the target data from the target physical address of the second memory to an updated physical address of the first memory, and updating the page table to store a mapping between the target virtual address of the target data and the updated physical address to the first memory.
6 . The method of claim 3 , further comprising:
selecting a victim memory block stored in an updated target physical address in the storage-side DRAM;
copying the victim memory block to the one or more memory channels;
storing a target memory block corresponding to the target physical address in place of the victim memory block in the storage-side DRAM; and
updating the page table of the storage-side DRAM to include a mapping between the target virtual address and the updated target physical address in the storage-side DRAM.
7 . The method of claim 1 , wherein after the page table is searched, the target physical address corresponding to the target virtual address is identified in a page table entry of the page table.
8 . The method of claim 1 , wherein:
the page table of the storage-side DRAM includes a supplemental page table;
a host-side DRAM of the host device is distinct from the storage-side DRAM; and
the host-side DRAM has a host page table.
9 . The method of claim 8 , further comprising, in response to the memory access request and prior to searching the supplemental page table:
searching the host page table stored in the host-side DRAM for the target physical address mapped to the target virtual address of the target data, wherein the host page table includes mappings between a plurality of virtual addresses and a plurality of physical addresses of the host-side DRAM;
wherein the supplemental page table is searched in accordance with a page table miss in the host page table.
10 . The method of claim 1 , wherein:
a host-side DRAM of the host device further includes a page directory that is a higher level of the page table;
the page directory further includes a target directory entry indicating that the page table mapping the target physical address and the target virtual address is located in the memory system; and
the page table of the storage-side DRAM is searched in response to identifying the target directory entry in the page directory of the host-side DRAM.
11 . The method of claim 10 , wherein the host-side DRAM uses a first double data rate (DDR) interface, and the storage-side DRAM uses a second DDR interface that is distinct from the first DDR interface.
12 . A memory system, comprising:
a memory controller configured to receive a memory access request for target data stored in the memory system, wherein the memory access request further includes a target virtual address of the target data;
a storage-side DRAM coupled to the memory controller and including a page table, wherein the page table includes mappings between a plurality of virtual addresses and a plurality of physical addresses, and the storage-side DRAM is configured to in response to the memory access request, search the page table stored in the storage-side DRAM for a target physical address mapped to the target virtual address of the target data; and
one or more memory channels coupled to the memory controller, wherein the storage-side DRAM and the one or more memory channels are configured to provide the target data based on a search result;
wherein the memory system is coupled to a host device including a translation lookaside buffer (TLB) that stores a plurality of recent translations of virtual addresses to physical addresses, and the host device is configured to, after extracting the target data, store a first recent translation of the target virtual address to the target physical address of the memory system among the plurality of recent translations in the TLB.
13 . The memory system of claim 12 , wherein the memory system is configured for:
identifying a hot memory block in the one or more memory channels;
migrating the hot memory block into an updated physical address of the storage-side DRAM; and
updating the page table of the storage-side DRAM to include a mapping between a virtual address and the updated physical address in the storage-side DRAM.
14 . The memory system of claim 12 , wherein the search result includes a page table hit, and extracting the target data further comprises, in accordance with the page table hit:
identifying the target physical address corresponding to the target virtual address in the storage-side DRAM based on the page table; and
extracting the target data that is stored in the storage-side DRAM according to the target physical address.
15 . The memory system of claim 12 , wherein the search result includes a page table miss, and extracting the target data further comprises, in accordance with the page table miss:
identifying the target physical address corresponding to the target virtual address in the one or more memory channels; and
extracting the target data that is stored in the one or more memory channels according to the target physical address.
16 . The memory system of claim 12 , wherein the search result includes a page table hit, and extracting the target data further comprises, in accordance with the page table hit:
identifying the target physical address corresponding to the target virtual address in the storage-side DRAM based on the page table; and
extracting the target data that is stored in the storage-side DRAM according to the target physical address.
17 . An electronic system, comprising:
a memory system configured to:
receive a memory access request for target data stored in the memory system, wherein the memory access request includes a target virtual address of the target data, and the memory system includes a storage-side DRAM and one or more memory channels; and
in response to the memory access request:
search a page table of the storage-side DRAM for a target physical address mapped to the target virtual address of the target data, wherein the page table includes mappings between a plurality of virtual addresses and a plurality of physical addresses; and
based on a search result, extract the target data stored in one of the storage-side DRAM and the one or more memory channels according to the target physical address in the page table; and
a host device coupled to the memory system and including one or more processors, wherein the host device includes a translation lookaside buffer (TLB) that stores a plurality of recent translations of virtual addresses to physical addresses, and is configured to, after extracting the target data, store a first recent translation of the target virtual address to the target physical address of the memory system among the plurality of recent translations in the TLB.
18 . The electronic system of claim 17 , wherein the electronic system is configured for:
identifying a hot memory block in the memory system;
identifying a victim memory block at an updated physical address in a host-side DRAM distinct from the memory system;
migrating the victim memory block to the memory system;
migrating the hot memory block into the updated physical address of the host-side DRAM; and
updating a page table of the host-side DRAM to include a mapping between a virtual address and the updated physical address in the host-side DRAM.
19 . The electronic system of claim 17 , wherein the memory system is coupled to the host device via a computer express link (CXL) that operates in compliance with a high-speed computer interconnect interface standard.
20 . The electronic system of claim 17 , wherein:
the page table of the storage-side DRAM includes a supplemental page table;
the host device includes a host-side DRAM, and the host-side DRAM is distinct from the storage-side DRAM; and
the host-side DRAM has a host page table.