Methods and apparatus for workflow processing

1 . A method, comprising:

receiving a workflow queue entry (WQE) that includes a key value;

searching a plurality of memory tables for an address that contains the key value;

when the address that contains the key value is found, obtaining a first queue identifier from the address;

when the address that contains the key value is not found, storing the key value and a second queue identifier at a selected address in a selected memory table;

storing the WQE in an aggregation queue identified by one of the first and second queue identifiers;

updating a count associated with the aggregation queue;

when the count reached a selected level, aggregating all WQE entries in the aggregation queue to form a WQE vector (VWQE);

accessing the selected address at all memory tables to obtain respective memory content;

comparing the respective memory content to determine an oldest memory content;

identifying one memory table that has the oldest memory content as the selected memory table;

obtaining an old queue identifier stored with the oldest memory content;

aggregating all WQE entries in an aggregation queue identified by the old queue identifier to form an old WQE vector (VWQE); and

outputting the old VWQE to a downstream processing system.

2 . The method of claim 1 , wherein the plurality of memory tables comprise “N” memory tables formed in an SRAM memory.

3 . The method of claim 2 , wherein the N memory tables comprise four memory tables.

4 . The method of claim 1 , further comprising updating a timestamp stored with the key value.

5 . The method of claim 1 , further comprising hashing the key value using a cuckoo hashing algorithm to generate 8-bits that forms the selected address.

6 . The method of claim 1 , wherein the operation of aggregating all WQE entries further comprises clearing the count.

7 . The method of claim 1 , further comprising receiving the WQE in a transmission from a client over a communication network.

8 . The method of claim 1 , further comprising outputting the VWQE to a downstream processing system.

9 . An apparatus, comprising:

an interface configured to receive a workflow queue entry (WQE) that includes a key value;

a plurality of memory tables;

an aggregation table having one or more aggregation queues; and

a processor configures to perform operations of:

searching the plurality of memory tables for an address that contains the key value;

when the address that contains the key value is found, obtaining a first queue identifier from the address;

when the address that contains the key value is not found, storing the key value and a second queue identifier at a selected address in a selected memory table;

storing the WQE in an aggregation queue identified by one of the first and second queue identifiers;

updating a count associated with the aggregation queue; and

when the count reached a selected level, aggregating all WQE entries in the aggregation queue to form a WQE vector (VWQE);

accessing the selected address at all memory tables to obtain respective memory content;

comparing the respective memory content to determine an oldest memory content;

identifying one memory table that has the oldest memory content as the selected memory table;

obtaining an old queue identifier stored with the oldest memory content;

aggregating all WQE entries in an aggregation queue identified by the old queue identifier to form an old WQE vector (VWQE); and

outputting the old VWQE to a downstream processing system.

10 . The apparatus of claim 9 , wherein the plurality of memory tables comprise “N” memory tables formed in an SRAM memory.

11 . The apparatus of claim 10 , wherein the N memory tables comprise four memory tables.

12 . The apparatus of claim 9 , wherein the processor updates a timestamp stored with the key value.

13 . The apparatus of claim 9 , wherein the processor performs a cuckoo hashing algorithm to hash the key value to generate 8-bits that forms the selected address.

14 . The apparatus of claim 9 , wherein the operation of aggregating all WQE entries further comprises clearing the count.

15 . The apparatus of claim 9 , wherein the interface receives the WQE in a transmission from a client over a communication network.

16 . The apparatus of claim 9 , further comprising an output interface that outputs the VWQE to a downstream processing system.

17 . A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation for data transmission via a communication network, wherein the HDL design structure comprises:

an interface configured to receive a workflow queue entry (WQE) that includes a key value;

a plurality of memory tables;

an aggregation table having one or more aggregation queues; and

a processor configures to perform operations of:

searching the plurality of memory tables for an address that contains the key value;

when the address that contains the key value is found, obtaining a first queue identifier from the address;

when the address that contains the key value is not found, storing the key value and a second queue identifier at a selected address in a selected memory table;

storing the WQE in an aggregation queue identified by one of the first and second queue identifiers;

updating a count associated with the aggregation queue;

when the count reached a selected level, aggregating all WQE entries in the aggregation queue to form a WQE vector (VWQE);

accessing the selected address at all memory tables to obtain respective memory content;

comparing the respective memory content to determine an oldest memory content;

identifying one memory table that has the oldest memory content as the selected memory table;

obtaining an old queue identifier stored with the oldest memory content;

aggregating all WQE entries in an aggregation queue identified by the old queue identifier to form an old WQE vector (VWQE); and

outputting the old VWQE to a downstream processing system.

18 . The HDL design structure of claim 17 , wherein the plurality of memory tables comprise “N” memory tables formed in an SRAM memory.

19 . The HDL design structure of claim 18 , wherein the N memory tables comprise four memory tables.

20 . The HDL design structure of claim 17 , wherein the processor updates a timestamp stored with the key value.

21 . The HDL design structure of claim 17 , wherein the processor performs a cuckoo hashing algorithm to hash the key value to generate 8-bits that forms the selected address.