Method for sharing a storage device among multiple processors and associated electronic device

1 . A method for sharing a storage device among multiple processors, comprising:

controlling a first processor among the multiple processors to operate in an access mode, and controlling a second processor among the multiple processors to operate in a detection mode;

in response to the first processor operating in the access mode, utilizing the first processor to control a logic value of a busy signal, to indicate that the first processor has permission to access the storage device, wherein the busy signal is a single-bit signal;

in response to at least one first predetermined condition, controlling the first processor to enter the detection mode from the access mode;

in response to at least one second predetermined condition, controlling the second processor to enter the access mode from the detection mode; and

in response to the second processor operating in the access mode, utilizing the second processor to control the logic value of the busy signal, to indicate that the second processor has the permission to access the storage device;

wherein utilizing the first processor to control the logic value of the busy signal to indicate that the first processor has the permission to access the storage device in response to the first processor operating in the access mode comprises:

in response to the first processor operating in the access mode, utilizing the first processor to pull the busy signal from a first logic value to a second logic value;

wherein controlling the first processor to enter the detection mode from the access mode in response to the at least one first predetermined condition comprises:

starting counting time at a time point of the first processor pulling the busy signal from the first logic value to the second logic value, to generate an access time;

wherein the first processor comprises a first state machine and a first signal control circuit; in response to the first state machine being unable to release the busy signal back to the first logic value in response to the access time reaching a predetermined access time threshold, the first signal control circuit forces the first processor to enter the detection mode from the access mode in response to the access time reaching a maximum access time threshold, in order to make the busy signal be released back to the first logic value from the second logic value; and the maximum access time threshold is greater than the predetermined access time threshold.

2 . The method of claim 1 , wherein the first processor and the second processor are alternately switched between the access mode and the detection mode, to make the first processor and the second processor control the logic value of the busy signal by turns.

3 . The method of claim 1 , wherein

the first state machine controls the first processor to enter the detection mode from the access mode in response to the access time reaching the predetermined access time threshold.

4 . The method of claim 1 , wherein

the first signal control circuit controls the first processor to enter the detection mode from the access mode in response to the first processor not sending any access instruction and the access time reaching a minimum access time threshold, in order to make the busy signal be released back to the first logic value from the second logic value.

5 . The method of claim 1 , wherein controlling the second processor to enter the access mode from the detection mode in response to the at least one second predetermined condition comprises:

starting counting time at a time point of the first processor releasing the busy signal back to the first logic value from the second logic value, to generate a debounce time;

wherein the second processor comprises a second state machine, and the second state machine controls the second processor to enter the access mode from the detection mode in response to the debounce time reaching a debounce time threshold.

6 . The method of claim 1 , wherein controlling the second processor to enter the access mode from the detection mode in response to the at least one second predetermined condition comprises:

starting counting time at a time point of the second processor starting operating in the detection mode, to generate a detection time;

wherein the second processor comprises a second signal control circuit, and the second signal control circuit controls the second processor to enter the access mode from the detection mode in response to the detection time reaching a detection time threshold, in order to pull the busy signal from the first logic value to the second logic value.

7 . The method of claim 1 , wherein an electronic device comprises the multiple processors and the storage device, an update equipment writes an updated program code into the storage device to perform a firmware update of the electronic device during a period of the first processor operating in the access mode, and the method further comprises:

after the updated program code is completely written into the storage device, utilizing the update equipment to perform a soft reset on the first processor, and releasing the busy signal back to the first logic value from the second logic value; and

utilizing at least one counter of the second processor to start counting time at a time point of starting the firmware update to generate an update time, and performing the soft reset of the second processor in response to the update time reaching an update time threshold and the busy signal being released back to the first logic value from the second logic value.

8 . The method of claim 1 , wherein the first processor comprises at least one first counter, the second processor comprises at least one second counter, the at least one first counter performs counting time based on a clock signal, and the at least one second counter performs counting time based on the clock signal.

9 . An electronic device, comprising:

a storage device, storing data and a program code; and

multiple processors, coupled to the storage device, controlling operations of the electronic device according to the data or the program code stored in the storage device, wherein:

when a first processor among the multiple processors operates in an access mode, a logic value of a busy signal is controlled by the first processor, to indicate that the first processor has permission to access the storage device, and a second processor among the multiple processors operates in a detection mode, wherein the busy signal is a single-bit signal;

when an operation of the first processor meets at least one first predetermined condition, the first processor enters the detection mode from the access mode; and

when an operation of the second processor meets at least one second predetermined condition, the second processor enters the access mode from the detection mode, wherein when the second processor operates in the access mode, the logic value of the busy signal is controlled by the second processor, to indicate that the second processor has the permission to access the storage device;

wherein when the first processor operates in the access mode, the first processor pulls the busy signal from a first logic value to a second logic value;

wherein the first processor comprises:

at least one first counter, starting counting time at a time point of the first processor pulling the busy signal from the first logic value to the second logic value, to generate an access time; and

a first signal control circuit, wherein when a first state machine is unable to release the busy signal back to the first logic value in response to the access time reaching a predetermined access time threshold, the first signal control circuit forces the first processor to enter the detection mode from the access mode in response to the access time reaching a maximum access time threshold, in order to make the busy signal be released back to the first logic value from the second logic value, wherein the maximum access time threshold is greater than the predetermined access time threshold.

10 . The electronic device of claim 9 , wherein the first processor and the second processor are alternately switched between the access mode and the detection mode, to make the first processor and the second processor control the logic value of the busy signal by turns.

11 . The electronic device of claim 9 , wherein the first processor comprises:

the first state machine, controlling the first processor to enter the detection mode from the access mode in response to the access time reaching the predetermined access time threshold.

12 . The electronic device of claim 9 , wherein

the first signal control circuit controls the first processor to enter the detection mode from the access mode in response to the first processor not sending any access instruction and the access time reaching a minimum access time threshold, in order to make the busy signal be released back to the first logic value from the second logic value.

13 . The electronic device of claim 9 , wherein the second processor comprises:

at least one second counter, starting counting time at a time point of the first processor releasing the busy signal back to the first logic value from the second logic value, to generate a debounce time; and

a second state machine, controlling the second processor to enter the access mode from the detection mode in response to the debounce time reaching a debounce time threshold.

14 . The electronic device of claim 9 , wherein the second processor comprises:

at least one second counter, starting counting time at a time point of the second processor starting operating in the detection mode, to generate a detection time; and

a second signal control circuit, controlling the second processor to enter the access mode from the detection mode in response to the detection time reaching a detection time threshold, in order to pull the busy signal from the first logic value to the second logic value.

15 . The electronic device of claim 9 , wherein an update equipment writes an updated program code into the storage device to perform a firmware update of the electronic device during a period of the first processor operating in the access mode; after the updated program code is completely written into the storage device, the update equipment performs a soft reset on the first processor to release the busy signal back to the first logic value from the second logic value; and at least one second counter of the second processor starts counting time at a time point of the firmware update being started, to generate an update time, and the soft reset of the second processor is performed in response to the update time reaching an update time threshold and the busy signal being released back to the first logic value from the second logic value.