Memory devices with multiple pseudo-channels
A memory module is provided, comprising a connector and a plurality of memory devices. Each memory device includes a memory array and a plurality of data connections, wherein a first subset of the plurality of data connections are configured to communicate data with a first portion of the memory array, and a second subset of the plurality of data connections are configured to communicate data with a second portion of the memory array. The first subset of the plurality of data connections of each of the plurality of memory devices are connected in parallel to first external contacts of the connector in a first addressable pseudo-channel, and the second subset of the plurality of data connections of each of the plurality of memory devices are connected in parallel to second external contacts of the connector in a second addressable pseudo-channel.
1 . An apparatus comprising:
a connector; and
a plurality of memory devices, each of the memory devices having a memory array, a command/address bus having a plurality of command/address connections, and a set of data connections, wherein a first subset of the set of data connections is configured to communicate data with a first portion of the memory array, and a second subset of the set of data connections is configured to communicate data with a second portion of the memory array, and wherein each of the plurality of command/address connections in the command/address bus are coupled to both the first portion of the memory array in a first addressable pseudo-channel and to the second portion of the memory array in a second addressable pseudo-channel;
wherein data connections of the first subset of each memory device of the plurality of memory devices are connected in parallel to first external contacts of the connector in the first addressable pseudo-channel, and
wherein data connections of the second subset of each memory device of the plurality of memory devices are connected in parallel to second external contacts of the connector in the second addressable pseudo-channel.
2 . The apparatus of claim 1 , wherein each memory device of the plurality of memory devices includes a plurality of data strobe connections that are each coupled both to the first portion of the memory array and to the second portion of the memory array.
3 . The apparatus of claim 1 , further comprising a registering clock driver coupled between the connector and the command/address bus of each memory device of the plurality of memory devices.
4 . The apparatus of claim 1 , wherein the plurality of memory devices comprises:
a first set of memory devices configured to store data, and
a second set of memory devices configured to store error detection and/or correction metadata corresponding to the data.
5 . The apparatus of claim 4 , wherein the second set contains only a single memory device.
6 . The apparatus of claim 1 , wherein the plurality of memory devices comprises dynamic random-access memory (DRAM) devices.
7 . The apparatus of claim 1 , wherein the connector is an edge connector of a dual in-line apparatus (DIMM).
8 . An apparatus comprising:
a plurality of memory devices, each of the plurality of memory devices having a memory array, a plurality of command/address connections, and a set of data connections, wherein a first subset of the set of data connections is configured to communicate data with a first portion of the memory array, and a second subset of the set of data connections is configured to communicate data with a second portion of the memory array, and wherein each of the plurality of command/address connections are each coupled to both the first portion of the memory array and to the second portion of the memory array;
wherein the apparatus is configured to perform a first data communication with the first subset of each memory device of the plurality of memory devices and a second data communication with the second subset of each memory device of the plurality of memory devices, wherein the first data communication and the second data communication overlap in time.
9 . The apparatus of claim 8 , wherein the first data communication is offset from the second data communication by a delay corresponding to a duration of a command to perform the second data communication.
10 . The apparatus of claim 8 , wherein each memory device of the plurality of memory devices includes a plurality of data strobe connections that are each coupled both to the first portion of the memory array and to the second portion of the memory array.
11 . The apparatus of claim 8 , further comprising a registering clock driver coupled between a connector and the plurality of command/address connections of each memory device of the plurality of memory devices.
12 . The apparatus of claim 8 , wherein the plurality of memory devices comprises:
a first set of memory devices configured to store data, and
a second set of memory devices configured to store error detection and/or correction metadata corresponding to the data.
13 . The apparatus of claim 8 , wherein the first data communication and the second data communication are either both read operations or both write operations.
14 . A method comprising:
receiving a first command to perform a first data communication;
in response to the first command,
routing the first command to a first portion of a memory array of each memory device of a plurality of memory devices via a plurality of command/address busses individually corresponding to the plurality of memory devices; and
communicating data concurrently with the first portion of the memory array of each memory device of the plurality of memory devices via a first subset of a set of data connections of each memory device of the plurality of memory devices;
receiving a second command to perform a second data communication; and
in response to the second command,
routing the second command to a second portion of the memory array of each memory device of the plurality of memory devices via the plurality of command/address busses individually corresponding to the plurality of memory devices; and
communicating data concurrently with a second portion of the memory array of each memory device of the plurality of memory devices via a second subset of the set of data connections of each of the plurality of memory devices.
15 . The method of claim 14 , wherein communicating data with the first portion of the memory array of each memory device of the plurality of memory devices overlaps in time with communicating data with the second portion of the memory array of each memory device of the plurality of memory devices.
16 . The method of claim 14 , wherein communicating data with the first portion of the memory array of each memory device of the plurality of memory devices and communicating data with the second portion of the memory array of each memory device of the plurality of memory devices comprises either two read operations or two write operations.
17 . The method of claim 14 , wherein communicating data with the first portion of the memory array of each memory device of the plurality of memory devices is offset from communicating data with the second portion of the memory array of each memory device of the plurality of memory devices by a delay corresponding to a duration of the second command.
18 . The method of claim 14 , wherein the data comprises user data stored in a first subset of the plurality of memory devices and error detection and/or correction metadata stored in a second subset of the plurality of memory devices.