Message conversion and message passthrough between devices and a processor in a multi-panel computing device

1 . A system comprising:

a first processor disposed within a lid portion of a computing device including a screen, the first processor communicatively coupled to a plurality of input/output (I/O) devices according to a plurality of I/O communication protocols via a first number of wires;

a second processor in a base portion of the computing device and communicatively coupled to the first processor by a bus containing a second number of wires, wherein the second number of wires is less than the first number of wires; and

a first memory disposed within the lid portion and coupled to the first processor to store first instructions that, when executed by the first processor, cause the first processor to:

receive, from a first I/O device of the plurality of I/O devices, a first message according to a first I/O communication protocol of the plurality of I/O communication protocols;

convert the first message to a second message, wherein the second message is a packet according to a host communication protocol, wherein to convert the first message to the second message is to include encapsulating, in the packet, the first message according to the first I/O communication protocol, a transaction type of the first message, and a protocol type indicating the first I/O communication protocol of the first message encapsulated in the packet; and

send the second message over the bus to the second processor, wherein the bus traverses a hinge movably coupling the lid portion to the base portion.

2 . The system of claim 1 , wherein the first processor is communicatively coupled to a human interface device (HID) according to a first HID communication protocol via a third number of wires.

3 . The system of claim 2 , wherein the first memory is to store second instructions that, when executed by the first processor, cause the first processor to:

receive a third message according to the first HID communication protocol from the human interface device, wherein the third message is to contain input data; and

generate a fourth message according to a second HID communication protocol, the fourth message to contain the input data, wherein the second message of the host communication protocol and the fourth message of the second HID communication protocol are to be multiplexed onto the second number of wires traversing the hinge.

4 . The system of claim 3 , wherein the second instructions, when executed by the first processor, cause the first processor further to, prior to generating the fourth message:

extract the input data from the third message; and

run a touch optimization algorithm to optimize the input data.

5 . The system of claim 3 , wherein the second HID communication protocol is a HID over universal serial bus (HID over USB) protocol or a HID over peripheral component interconnect (PCIe) protocol (HID over PCIe), and wherein the first HID communication protocol is a HID over serial peripheral interface (HID over SPI) protocol or a HID over inter-integrated circuit (HID over I2C) protocol.

6 . The system of claim 1 ,

wherein the second processor is coupled to a second memory, wherein the second memory is to store operating system instructions that, when executed by the second processor, cause the second processor to:

receive the second message from the first processor;

determine the protocol type of the first message encapsulated in the packet; and

in response to determining that the protocol type of the first message encapsulated in the packet corresponds to the first I/O communication protocol, convert the second message to the first message according to the first I/O communication protocol.

7 . The system of claim 6 , wherein the operating system instructions, when executed by the second processor, are to cause the second processor further to:

determine that the second message is associated with a first logical function corresponding to the first instructions or a second logical function corresponding to second instructions stored in the first memory coupled to the first processor; and

determine the protocol type of the first message encapsulated in the packet in response to determining that the second message is associated with the first logical function corresponding to the first instructions.

8 . The system of claim 6 , wherein the operating system instructions, when executed by the second processor, are to cause the second processor further to:

provide the first message according to the first I/O communication protocol to a virtual input/output (I/O) driver corresponding to the first I/O communication protocol to enable a software application running on the second processor to access the first message from one or more virtual pins exposed by the virtual I/O driver, wherein the one or more virtual pins are associated with the first I/O communication protocol.

9 . The system of claim 1 , wherein the first I/O communication protocol is one of a serial peripheral interface (SPI), a general peripheral input/output (GPIO), an inter-integrated circuit (I2C), or a universal asynchronous receiver-transmitter (UART), and wherein the host communication protocol is either a universal serial bus (USB) or a peripheral component interconnect express (PCIe).

10 . The system of claim 1 , wherein the plurality of I/O devices includes two or more of a camera, an electric shutter, a sensor, a microphone, and a light-emitting diode (LED).

11 . An apparatus, comprising:

a first processor;

a first plurality of pins configured to be communicatively coupled to a plurality of input/output (I/O) devices by a first plurality of wires, wherein the plurality of I/O devices are disposed in a first portion of a computing device and are associated with a plurality of input/output (I/O) communication protocols, respectively;

a second plurality of pins configured to be communicatively coupled to a second processor by a second plurality of wires, wherein the second processor is disposed in a second portion of the computing device and is associated with a second communication protocol; and

memory coupled to the first processor, the memory to store first instructions that, when executed by the first processor, cause the first processor to:

receive a first message from a first I/O device of the plurality of I/O devices according to a first I/O communication protocol of the plurality of I/O communication protocols;

convert the first message to a second message, wherein the second message is a packet based on the second communication protocol, wherein to convert the first message to the second message is to include encapsulating, in the packet, the first message according to the first I/O communication protocol, a transaction type of the first message, and a protocol type identifying the first I/O communication protocol of the first message encapsulated in the packet; and

send the second message to the second processor via the second plurality of wires, wherein the second plurality of wires includes fewer wires than the first plurality of wires.

12 . The apparatus of claim 11 , further comprising:

a third plurality of pins to support a first human interface device (HID) communication protocol associated with a third plurality of wires to communicatively couple the first processor to a human interface device.

13 . The apparatus of claim 12 , wherein the memory is to store second instructions that, when executed by the first processor, cause the first processor to:

receive a third message according to the first HID communication protocol from the human interface device, wherein the third message is to contain input data; and

generate a fourth message according to a second HID communication protocol, the fourth message to contain the input data, wherein the second message of the second communication protocol and the fourth message of the second HID communication protocol are to be multiplexed onto the second plurality of wires to traverse a hinge movably coupling the first portion to the second portion.

14 . The apparatus of claim 13 , wherein the second instructions, when executed by the first processor, cause the first processor to:

in response to receiving a first host power state command in a fifth message according to the second HID communication protocol via the second plurality of wires, identify a first HID power state command corresponding to the first host power state command based on power state command information, the power state command information including one or more HID power state commands associated with the human interface device mapped to one or more host power state commands associated with the second HID communication protocol.

15 . The apparatus of claim 11 , wherein the first I/O communication protocol is one of a serial peripheral interface (SPI), a general peripheral input/output (GPIO), an inter-integrated circuit (I2C), or a universal asynchronous receiver-transmitter (UART), and wherein the second communication protocol is one of a universal serial bus (USB) or a peripheral component interconnect express (PCIe).

16 . The apparatus of claim 11 , wherein the computing device includes a foldable screen disposed in the first portion and the second portion, the first portion and the second portion being foldable relative to each other.

17 . The apparatus of claim 11 , wherein the first portion is a lid portion including a screen, and wherein the second portion is a base portion movably connected to the lid portion.

18 . One or more non-transitory machine readable media comprising instructions for execution that when executed by a first processor, cause the first processor to:

receive, from a first input/output (I/O) device of a plurality of I/O devices in a lid portion of a computing device including a screen, a first message according to a first I/O communication protocol of a plurality of I/O communication protocols associated with a first plurality of wires to connect the first processor to the plurality of I/O devices;

convert the first message to a second message, wherein the second message is a packet based on a host communication protocol associated with a second plurality of wires to connect the first processor to a second processor in a base portion of the computing device, wherein to convert the first message to the second message is to include encapsulating, in the packet, the first message according to the first I/O communication protocol, a transaction type of the first message, and a protocol type that indicates the first I/O communication protocol of the first message encapsulated in the packet; and

send the second message over the second plurality of wires to traverse a hinge movably coupling the lid portion and the base portion, wherein the second plurality of wires includes fewer wires than the first plurality of wires.

19 . The one or more non-transitory machine readable media of claim 18 , wherein the first message according to the first I/O communication protocol is contained in a payload portion of the packet, the transaction type is contained in a metadata portion of the packet, and the protocol type is contained in the metadata portion of the packet.

20 . The apparatus of claim 11 , wherein the first message according to the first I/O communication protocol is contained in a payload portion of the packet, the transaction type is contained in a metadata portion of the packet, and the protocol type is contained in the metadata portion of the packet.