IP Library › Granted Patent US 12664117
Granted Patent B2
US 12664117 · App. 17/950,925 · Granted Jun 23, 2026

Disaggregated memory server

Inventors: Krishna Teja Malladi (San Jose, CA); Byung Hee Choi (Fremont, CA); Andrew Chang (Los Altos, CA); Ehsan M. Najafabadi (San Jose, CA)
Assignee: Samsung Electronics Co., Ltd.
G06F13/4027G06F3/0604G06F3/0619G06F3/0625G06F3/0629G06F3/0647G06F3/0653G06F3/0659G06F3/067G06F3/0679G06F9/4401G06F12/0802G06F12/0808G06F12/1045G06F13/1663G06F13/28G06F13/4022G06F13/4068G06F13/409G06F13/4221G06F15/17331H04L49/45G06F2212/621G06F2213/0026G06F2213/28H04L49/351
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Quick Facts
Patent No.
US 12664117
App. No.
17/950,925
Granted
Jun 23, 2026
Kind
B2
Abstract

A system and method for managing memory resources. In some embodiments, the system includes a first memory server, a second memory server, and a server-linking switch connected to the first memory server and to the second memory server. The first server may include a cache-coherent switch and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, and the cache-coherent switch is connected to the server-linking switch.

Claims (52)

1 . A system, comprising:

a first server, comprising:

a processor;

a first switch including a procession element; and

a first memory device; and

a second switch connected to the first server,

wherein:

the first memory device is connected to the first switch via a first interface, and

the first switch is connected to the second switch via a second interface different from the first interface.

2 . The system of claim 1 , wherein the second switch is configured to alter an attribute of the first memory device, wherein the attribute includes power to the first memory device.

3 . The system of claim 2 , wherein:

the second switch is configured to alter power to the first memory device by instructing the first switch to alter the power to the first memory device, and

the first switch is configured to alter the power to the first memory device based on instructions from the second switch.

4 . The system of claim 1 , wherein the first switch is configured to identify data within the first memory device that satisfies a criterion.

5 . The system of claim 1 , wherein the first switch is configured to compress data and to store compressed data in the first memory device.

6 . The system of claim 1 , wherein the second switch is configured to query a status of the first server.

7 . The system of claim 6 , wherein the first switch is configured to query a status of the first server through an interface connected to the first server.

8 . The system of claim 7 , wherein the querying of the status comprises querying at least one of a power status, a network status, or an error check status.

9 . The system of claim 1 , wherein the second switch is configured to batch cache requests directed to the first server.

10 . The system of claim 1 , further comprising a second server connected to the second switch, wherein the second switch is configured to maintain, between first data stored on the first server and second data stored on the second server, a consistency level.

11 . The system of claim 1 , wherein the first switch is configured to:

monitor a property of a first region of memory, and

move data from the first region of memory to a second region of memory,

wherein:

the first region of memory is a memory of a first type, and

the second region of memory is a memory of a second type.

12 . The system of claim 1 , wherein the second switch comprises a Peripheral Component Interconnect Express (PCIe) switch.

13 . The system of claim 1 , wherein the second switch comprises a Compute Express Link (CXL) switch.

14 . The system of claim 13 , wherein the second switch comprises a top of rack (ToR) CXL switch.

15 . The system of claim 1 further comprising a second server, wherein the second switch is configured to transmit data from the second server to the first server, and to perform flow control on the data.

16 . The system of claim 1 , further comprising a second server and a third server connected to the second switch, wherein:

the second switch is configured to:

receive a first packet, from the second server,

receive a second packet, from the third server, and

transmit the first packet and the second packet to the first server.

17 . A method for accessing memory in a computing system, the method comprising:

receiving, by a second switch, a first packet, from a second server, wherein the second switch is connected to a first server and to the second server, the second server comprising a stored-program processing circuit, and the first server comprising a processor, a first switch including a processing element, and a first memory device, wherein the first memory device is connected to the first switch via a first interface, the first switch is connected to the second switch via a second interface different from the first interface, and wherein the second switch is configured to alter an attribute of the first memory device; and

transmitting the first packet to the first server.

18 . The method of claim 17 , further comprising:

compressing data, by the first switch, and

storing the data in the first memory device.

19 . The method of claim 17 , further comprising:

querying, by the second switch, a status of the first server.

20 . A system, comprising:

a server, comprising:

a processor;

a first switch including a processing element; and

a memory device; and

second switching means connected to the server,

wherein:

the memory device is connected to the first switch via a first interface, and

the first switch is connected to the second switching means via a second interface different from the first interface.