Communication system and communication method

1 . A communication system, comprising:

at least two communication channels, each of which comprises at least two chips coupled in series, wherein each chip comprises a communication input pin, a communication output pin, and at least one addressing pin, and electrical connections of the addressing pin in the chip comprise one of floating, electrical coupling with the communication input pin of the chip, and electrical coupling with the communication output pin of the chip;

b) a master device configured to identify each communication channel according to level information of each addressing pin of at least a first chip in each communication channel, wherein the communication input pin of the first chip in each communication channel is connected to a same output port of the master device, and the addressing pin of each chip is not connected to the master device, and the addressing pin of each chip is not connected to the master device; and

c) wherein the addressing pins of the at least first chip in different communication channels perform different electrical connections such that each electrical connection of the addressing pin of the at least first chip in each communication channel corresponds to one column address of the corresponding communication channel.

2 . The system of claim 1 , wherein the connections of the addressing pin of the chip comprises at least three of coupling with a power supply terminal, coupling with a ground terminal, coupling with the communication input pin of the chip, coupling with the communication output pin of the chip, and floating.

3 . The system of claim 1 , wherein the addressing pins of the all chips in the same communication channel perform same connection, and the addressing pins of the chips in the different communication channels perform different connections.

4 . The system of claim 1 , wherein the addressing pins of the first chips in the different communication channels perform different connections.

5 . The system of claim 4 , wherein the addressing pins of a second chip to a last chip in the all communication channels perform a same connection.

6 . The system of claim 4 , wherein the addressing pins of a second chip to a last chip in the all communication channels perform arbitrary connections.

7 . The system of claim 1 , wherein:

a) the master device transmits an address configuration command, and each chip in the communication channel, when receiving the address configuration command serves as a current chip;

b) in each communication channel, the current chip receives the address configuration command from the master device or a previous chip to enter an address configuration time interval, and transmits the address configuration command to a next chip; and

c) each chip in the address configuration time interval obtains a column address of the chip according to the connection of each addressing pin of the chip.

8 . The system of claim 1 , wherein:

a) the master device transmits an address configuration command;

b) the first chip in each communication channel receives the address configuration command from the master device to enter an address configuration time interval; and

c) the first chip in the address configuration time interval obtains a column address of the first chip according to the connection of each addressing pin of the first chip.

9 . The system of claim 3 , wherein:

a) the master device transmits a communication data packet comprising column address data and row address data, and each chip in the communication channel when receiving the communication data packet serves as a current chip;

b) in each communication channel, the current chip receives the communication data packet from the master device or a previous chip, and respectively compares the column address data and the row address data in the communication data packet received by the current chip against the column address and a row address of the current chip;

a) when the column address data and the row address data respectively match the column address and the row address, the current chip serves as a target chip in the communication and implements corresponding commands in the communication data packet; and

b) when the column address data does not match the column address and/or the row address data does not match the row address, the current chip forwards the communication data packet received by the current chip to a next chip, wherein the current chip does not modify the column address data in the communication data packet received by the current chip.

10 . The system of claim 5 , wherein:

a) the master device transmits a communication data packet comprising column address data and row address data, and each chip in the communication channel when receiving the communication data packet serves as a current chip;

b) in each communication channel, the current chip receives the communication data packet from the master device or a previous chip, and respectively compares the column address data and the row address data in the communication data packet received by the current chip against the column address and a row address of the current chip;

c) when the column address data and the row address data respectively match the column address and the row address, the current chip serves as a target chip in the communication and implements corresponding commands in the communication data packet; and

d) when the column address data does not match the column address and/or the row address data does not match the row address, the current chip modifies the column address data in the communication data packet received by the current chip and forwards the modified communication data packet to a next chip.

11 . The system of claim 10 , wherein when coding of the column addresses the second chip to the last chip in the all communication channels is 0, a calculation method of modifying the column address data performed by the current chip comprises one of:

a) the current chip subtracts the column address of the current chip from the column address data in the communication data packet received by the current chip;

b) the current chip subtracts the column address data in the communication data packet received by the current chip from the column address of the current chip; and

c) the current chip performs XOR on the column address data in the communication data packet received by the current chip and the column address of the current chip.

12 . The system of claim 1 , wherein:

a) the master device transmits a communication data packet comprising column address data and row address data;

b) the first chip in each communication channel receives the communication data packet transmitted by the master device, and compares the column address data in the communication data packet against the column address of the first chip, wherein the communication channel serves as a current communication channel when the first chip of the communication channel receives the communication data packet;

c) when the column address data matches the column address, the current communication channel serves as a target communication channel in the communication, and addressing of the row address is performed on the chips in the target communication channel according to the row address data in the communication data packet; and

d) when the column address data does not match the column address, the current communication channel does not serve as the target communication channel in the communication, and the first chip in the current communication channel does not forward the communication data packet to the next chip.

13 . A communication method for a communication system comprising a master device and at least two communication channels, wherein each channel comprises at least two chips coupled in series, and each chip comprises a communication input pin, a communication output pin, and at least one addressing pin, the method comprising:

a) transmitting an address configuration command by the master device;

b) receiving the address configuration command by at least first chip in each communication channel to enter an address configuration time interval;

c) in the address configuration time interval, encoding a column address of the chip by the at least one first chip in each communication channel according to level information of each addressing pin of the chip, wherein electrical connections of the addressing pin in the chip comprises one of floating, electrical coupling with the communication input pin of the chip, and electrical coupling with the communication output pin of the chip, and wherein the addressing pins of the at least one first chip in each different communication channel perform different electrical connections such that each electrical connection of the addressing pin of the at least first chip in each communication channel corresponds to one column address of the corresponding communication channel;

d) transmitting a communication data packet and identifying each communication channel according to the column address of the at least one first chip in each communication channel by the master device; and

e) wherein the communication input pin of the first chip in each communication channel is connected to a same output port of the master device, and the addressing pin of each chip is not connected to the master device.

14 . The method of claim 13 , wherein the connections of the addressing pin of the chip comprises at least three of coupling with a power supply terminal, coupling with a ground terminal, coupling with the communication input pin of the chip, coupling with the communication output pin the chip, and floating.

15 . The method of claim 13 , wherein the addressing pins of the all chips in the same communication channel perform same connection, and the addressing pins of the chip in the different communication channels perform different connections.

16 . The method of claim 13 , wherein the addressing pins of the first chips in the different communication channels perform different connections, and the addressing pins of a second chip to a last chip in the all communication channels perform same connection.

17 . The method of claim 13 , wherein the addressing pins of the first chips in the different communication channels perform different connections, and the addressing pins of a second chip to a last chip in the all communication channels perform arbitrary connections.

18 . The method of claim 15 , further comprising:

a) transmitting a communication data packet comprising column address data and row address data by the master device, wherein each chip in the communication channel when receiving the communication data packet serves as a current chip;

b) receiving the communication data packet from the master device or a previous chip and respectively comparing the column address data and the row address data in the communication data packet received by the current chip with the column address and a row address of the current chip by the current chip in each communication channel;

c) when the column address data and the row address data respectively match the column address and the row address, regarding the current chip as a target chip in the communication and implementing corresponding commands in the communication data packet by the target chip; and

d) when the column address data does not match the column address and/or the row address data does not match the row address, forwarding the communication data packet received by the current chip to a next chip by the current chip, wherein the current chip does not modify the column address data in the communication data packet received by the current chip.

19 . The method of claim 16 , further comprising:

a) transmitting a communication data packet comprising column address data and row address data by the master device, wherein each chip in the communication channel when receiving the communication data packet serves as a current chip;

b) receiving the communication data packet from the master device or a previous chip and respectively comparing the column address data and the row address data in the communication data packet received by the current chip with the column address and a row address of the current chip by the current chip in each communication channel;

c) when the column address data and the row address data respectively match the column address and the row address, regarding the current chip as a target chip in the communication and implementing corresponding commands in the communication data packet by the target chip; and

d) when the column address data does not match the column address and/or the row address data does not match the row address, modifying the column address data in the communication data packet received by the current chip and forwarding the modified communication data packet to a next chip by the current chip.

20 . The method of claim 13 , further comprising, in the address configuration time interval, receiving a PWM signal by the communication input pin or the communication output pin of the chip to identify the connection that the addressing pin is coupled with the communication input pin or the communication output pin.