Scalar masking countermeasure
Generally discussed herein are devices, systems, and methods for secure elliptic curve cryptography (ECC) operation. A circuit can include a multiplier coupled to receive a radix of a group order and a radix of a random number and generate a product based on the group order and the random number, a first adder coupled to receive the product and contents of an accumulator and generate a sum based on the product and the contents, the accumulator coupled to receive the sum, and a second adder coupled to operate in parallel with the multiplier and the first adder, the second adder coupled to receive a radix of a secret key and a radix of the contents and generate a portion of a randomized secret key based on the secret key and the contents.
1 . An elliptic curve cryptography (ECC) countermeasure circuit comprising:
a multiplier coupled to receive a radix of a group order and a radix of a random number and generate a product based on the group order and the random number;
a first adder coupled to receive the product and contents of an accumulator and generate a sum based on the product and the contents;
the accumulator coupled to receive the sum; and
a second adder coupled to operate in parallel with the multiplier and the first adder, the second adder coupled to receive a radix of a secret key and a radix of the contents and generate a portion of a randomized secret key based on the secret key and the contents, the portion of the randomized secret key acts as a countermeasure from side channel analysis attacks.
2 . The ECC countermeasure circuit of claim 1 , wherein the accumulator is coupled to provide least significant bits of the contents as the radix of the contents to the second adder.
3 . The ECC countermeasure circuit of claim 2 , wherein the accumulator is coupled between the first adder and the second adder.
4 . The ECC countermeasure circuit of claim 3 , wherein the accumulator is configured to provide three radixes of the contents to the first adder.
5 . The ECC countermeasure circuit of claim 1 , wherein the radix is 32-bits.
6 . The ECC countermeasure circuit of claim 1 , wherein the portion is least significant bits in a first iteration and second least significant bits in a second iteration.
7 . The ECC countermeasure circuit of claim 1 , further comprising a shift register storing the secret key and an array register storing the group order and the random number.
8 . An elliptic curve cryptography (ECC) countermeasure method comprising:
generating, by a multiplier and coupled to receive a radix of a group order and a radix of a random number, a product based on the group order and the random number;
generating, by a first adder coupled to receive the product and contents of an accumulator, a sum based on the product and the contents;
receiving, by the accumulator, the sum; and
generating, by a second adder coupled to operate in parallel with the multiplier and the first adder and receive a radix of a secret key and a radix of the contents, a portion of a randomized secret key based on the secret key and the contents, the portion of the randomized secret key acts as a countermeasure from side channel analysis attacks.
9 . The method of claim 8 , further comprising providing, by the accumulator, least significant bits of the contents as the radix of the contents to the second adder.
10 . The method of claim 9 , wherein the accumulator is coupled between the first adder and the second adder.
11 . The method of claim 10 , wherein the accumulator is configured to provide three radixes of the contents to the first adder.
12 . The method of claim 8 , wherein the radix is 32-bits.
13 . The method of claim 8 , wherein the portion is least significant bits in a first iteration and second least significant bits in a second iteration.
14 . The method of claim 8 , further comprising:
storing, by a shift register, the secret key; and
storing, by an array register, the group order and the random number.
15 . An elliptic curve cryptography (ECC) system comprising:
an ECC countermeasure circuit comprising:
a multiplier coupled to receive a radix of a group order and a radix of a random number and generate a product based on the group order and the random number;
a first adder coupled to receive the product and contents of an accumulator and generate a sum based on the product and the contents; and
a second adder coupled to operate in parallel with the multiplier and the first adder, the second adder coupled to receive a radix of a secret key and a radix of the contents and generate a portion of a randomized secret key based on the secret key and the contents, the portion of the randomized secret key acts as a countermeasure from side channel analysis attacks; and
an ECC circuit coupled to receive the portion of the randomized secret key and implement ECC operations based on the portion of the randomized secret key.
16 . The ECC system of claim 15 , further comprising the accumulator, the accumulator coupled to receive the sum and provide least significant bits of the contents as the radix of the contents to the second adder.
17 . The ECC system of claim 16 , wherein the accumulator is coupled between the first adder and the second adder.
18 . The ECC system claim 17 , wherein the accumulator is configured to provide three radixes of the contents to the first adder.
19 . The ECC system of claim 15 , wherein the portion is least significant bits in a first iteration and second least significant bits in a second iteration.
20 . The ECC system of claim 15 , further comprising:
a shift register storing the secret key; and
an array register storing the group order and the random number.