Security in integrated circuits
An integrated circuit has multiple clock domains. At least one of the clock domains is a secure domain including a protection clock portion. The protection clock portion is arranged to produce a clock signal having a clock period which varies randomly over at least some cycles of operation. The clock signal is arranged to clock one or more components in the secure domain.
1 . An integrated circuit comprising:
a non-secure clock domain comprising a first clock portion arranged to generate a first clock signal, the first clock signal being arranged to clock one or more components in the non-secure clock domain; and
a secure clock domain comprising a protection clock portion arranged to, without receiving a clock signal from outside the secure clock domain, generate a protection clock signal having a clock period which varies randomly over at least some cycles of operation, said protection clock signal being arranged to clock one or more components in said secure clock domain,
wherein the protection clock portion comprises a plurality of delay elements and a selector register, the protection clock portion being configured to incorporate one or more of the plurality of delay elements according to a selection to form a delay chain, the selection being controlled by a respective bit of a selector value in the selector register; and
wherein the protection clock portion is arranged to update the selector register in successive cycles of operation with a new selector value, the new selector value being offset from a preceding selector value by an offset value, the offset value having a fixed magnitude and random polarity.
2 . An integrated circuit as claimed in claim 1 arranged to vary the clock period in every cycle of operation.
3 . An integrated circuit as claimed in claim 1 wherein the delay elements comprise standard cell-based unit delays.
4 . An integrated circuit as claimed in claim 1 wherein each delay element adds a delay which is twice the length of the delay added by the preceding element in the chain.
5 . An integrated circuit as claimed in claim 1 wherein each delay element is connected to a respective independent multiplexer and wherein each multiplexer is selectively controlled by a respective bit of a value in the selector register.
6 . An integrated circuit as claimed in claim 1 wherein the protection clock portion further comprises a static register comprising a lowest permitted value of the delay chain.
7 . An integrated circuit as claimed in claim 6 wherein the protection clock portion comprises an offset value generator arranged to generate a random variable which is added to said lowest permitted value to produce said selector value in said selector register.
8 . An integrated circuit as claimed in claim 7 wherein the protection clock portion comprises a pseudorandom bit sequence generator arranged to provide an input to the offset value generator to randomly increase or decrease the offset value generated thereby.
9 . An integrated circuit as claimed in claim 7 wherein the offset value generator comprises a feedback loop arranged to add a value to a previous offset value, such that a subsequent offset value for each clock cycle is only increased or decreased by 1.
10 . A method of preventing side-channel attacks on a secure clock domain of an integrated circuit comprising a non-secure clock domain and the secure clock domain, the method comprising:
generating a first clock signal in the first clock domain;
using the first clock signal to clock one or more components in the first clock domain;
generating a protection clock signal in the secure clock domain without receiving a clock signal from outside the secure clock domain, the protection clock signal having a clock period which varies randomly over at least some cycles of operation,
wherein generating the protection clock signal comprises incorporating one or more of a plurality of delay elements according to a selection to form a delay chain, the selection being controlled by a respective bit of a selector value in a selector register;
wherein the method comprises updating the selector register in successive cycles of operation with a new selector value, the new selector value being offset from a preceding selector value by an offset value, the offset value having a fixed magnitude and random polarity; and
using said protection clock signal to clock one or more components in said secure clock domain.