IP Library Granted Patent US 12664295
Granted Patent B2
US 12664295 · App. 18/121,190 · Granted Jun 23, 2026

Tamper and zeroization response unit

Inventors: James E Shaw (Ely, IA); Adrian A Hill (Cedar Rapids, IA); Michael A Steffen (Cedar Rapids, IA); Matt Seivert (Palo, IA); Alan High (Cedar Rapids, IA); William Byers (Marion, IA)
Assignee: Crystal Group, Inc.
G06F21/6218G06F21/602G06F21/81G06F21/88G06F21/86G06F2221/2143
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Quick Facts
Patent No.
US 12664295
App. No.
18/121,190
Granted
Jun 23, 2026
Kind
B2
Abstract

A device that encapsulates functions necessary to sanitize an electronic system after detecting tampering or when user zeroization occurs. The device includes a FPGA, sensors, external tamper sensors, a battery, interfaces or discrete signals required to execute sanitization of hard drives, flash, registers, etc. The device issues a sanitization response through interface commands Manual sanitization (zeroization) can be achieved two ways, locally or through a remote zeroize button/switch/discrete. The sanitization response is activated through monitoring the tamper sensors. The sanitization response will destroy stored data and encryption keys before they can be compromised. The sanitization response could produce a notification that an event has occurred. The system can provide data protection without main line or standby power. Sensors could include, chassis intrusion switches, motion detectors, radiation sensors, light sensors, temperature sensors, magnetic sensors, or other external inputs.

Claims (39)

1 . A system with reduced risk of unauthorized access to data in an electronic system, the electronic system comprising:

an electronic apparatus with:

a data storage device;

a processor;

a direct current power source;

wherein said direct current power source is electrically coupled to and provides power to both said processor and said data storage device;

a stand-alone tamper and zeroization response unit, wherein said stand-alone tamper and zeroization response unit is a data sanitization implement includes: (i) circuitry to detect tampering and automatically command a data sanitization, (ii) circuitry to allow a human to command data zeroization, and (iii) a battery therein for providing power to a data storage device for the purpose of zeroizing data therein when no power is being otherwise provided to the data storage device, coupled with said data storage device via a link which provides both power and a signal, to the data storage device for the purpose of sanitizing said data storage device; and

said link; never provides power to said processor, and is used to provide power to said data storage device irrespective of the operational state of said direct current power source.

2 . The system of claim 1 wherein said stand-alone tamper and zeroization response unit only provides power to said data storage device.

3 . The system of claim 2 wherein said stand-alone tamper and zeroization response unit receives data from said data storage device, when said direct current power source is not operational only during sanitization responses.

4 . The system of claim 3 wherein said stand-alone tamper and zeroization response unit has a battery therein, and said stand-alone tamper and zeroization response unit is configured so that said battery will be utilized exclusively for tamper detection, users zeroization commands and subsequent execution of sanitization procedures.

5 . The system of claim 4 , wherein the stand-alone tamper and zeroization response unit utilizes a discrete signal to exercise circuitry as part of a sanitization response which results in loss of power to volatile storage components, wiping stored data and/or encryption keys.

6 . The system of claim 1 , wherein the stand-alone tamper and zeroization response unit utilizes a discrete signal to exercise circuitry connected to said electronic apparatus as part of the sanitization response which results in said electronic apparatus executing a pre-existing internal sanitization procedure.

7 . The system of claim 1 , wherein the stand-alone tamper and zeroization response unit, issues software interface commands to said data storage device as part of a sanitization response which results in wiping of data and/or encryption keys stored on said data storage device.

8 . The system of claim 1 , where the stand-alone tamper and zeroization response unit allows a zeroization command to be issued through local or remote inputs.

9 . The system of claim 8 where the stand-alone tamper and zeroization response unit is configured so as to execute a sanitization response automatically when a tamper event occurs, or zeroization is commanded manually.

10 . The system of claim 9 where the stand-alone tamper and zeroization response unit is configured so as to utilize a battery to enable tamper detection, zeroization command, and sanitization response without an external power source.

11 . A method of sanitizing an electronic apparatus comprising the steps of:

providing a stand-alone tamper and zeroization response unit, wherein said stand-alone tamper and zeroization response unit is a data sanitization implement that includes: (i) circuitry to detect tampering and automatically command a data sanitization, (ii) circuitry to allow a human to command data zeroization, and (iii) a battery therein for providing power to a data storage device for the purpose of zeroizing data therein when no power is being otherwise provided to the data storage device;

electrically linking said stand-alone tamper and zeroization response unit to an electronic apparatus having therein:

an internal data storage device,

a microprocessor, and

a direct current power source:

providing a signal and power to said internal data storage device, via a link extending between said electronic apparatus and said stand-alone tamper and zeroization response unit; for the purpose of reducing unauthorized access to data stored on said internal data storage device;

wherein said link never provides power to said microprocessor; and

said direct current power source is electrically coupled to and provides power to both said microprocessor and said internal data storage device.

12 . The method of claim 11 , wherein said stand-alone tamper and zeroization response unit never receives power from said direct current power source.

13 . The method of claim 12 , wherein said stand-alone tamper and zeroization response unit never receives data from said internal data storage device, during normal operation.

14 . The method of claim 13 , wherein said stand-alone tamper and zeroization response unit has a battery therein that is sized, configured, and located so as to be utilized for tamper detection and subsequent creation and issuance of zeroization causing signals, during times when no external sources of power are being provided to said stand-alone tamper and zeroization response unit.

15 . The method of claim 14 , wherein the stand-alone tamper and zeroization response unit utilizes a discrete signal to exercise circuitry as part of a sanitization response which results in loss of power to volatile storage components, wiping stored data and/or encryption keys.

16 . The method of claim 11 , wherein the stand-alone tamper and zeroization response unit utilizes a discrete signal to exercise circuitry connected to said electronic apparatus as part of the sanitization response which results in said electronic apparatus executing a pre-existing internal sanitization procedure.

17 . The method of claim 11 , wherein the stand-alone tamper and zeroization response unit, issues software interface commands to said internal data storage device as part of a sanitization response which results in wiping of data and/or encryption keys stored on said internal data storage device.

18 . The method of claim 11 , where the stand-alone tamper and zeroization response unit allows a zeroization command to be issued through local or remote inputs.

19 . The method of claim 11 , where the stand-alone tamper and zeroization response unit is configured so as to execute a sanitization response automatically when a tamper event occurs, or zeroization is commanded manually.

20 . A method of sanitizing a data storage device comprising the steps of:

providing a stand-alone tamper and zeroization response unit;

wherein said stand-alone tamper and zeroization response unit is a data sanitization implement that includes: (i) circuitry to detect tampering and automatically command a data sanitization, (ii) circuitry to allow a human to command data zeroization, and (iii) a battery therein for providing power to a data storage device for the purpose of zeroizing data therein when no power is being otherwise provided to the data storage device;

monitoring sensors for tamper events, monitoring zeroization inputs, and initiating sanitization procedures in response thereto, and

where said steps of monitoring sensors for tamper events, monitoring zeroization inputs and initiation of sanitization procedures can be performed from battery power which is never used for any purpose other than said steps of monitoring sensors for tamper events, monitor zeroization inputs and sanitization procedures.