Data encryption suitable for use in systems with processing-in-memory
An encryption circuit includes an iterative block cipher circuit. The iterative block cipher circuit has a counter input for a row index, a key input for receiving a secret key, and an output for providing an encrypted counter value in response to performing a block cipher process using the row index as a counter the secret key. The encryption circuit uses the iterative block cipher circuit during a row operation to a memory.
1 . An encryption circuit, comprising:
an iterative block cipher circuit having a counter input for receiving a row index, a key input for receiving a secret key, and an output for providing an encrypted counter value in response to performing a block cipher process using said row index as a counter and said secret key; and
wherein the encryption circuit uses said iterative block cipher circuit to perform an iterative block cipher operation during a time period of a row activation operation to a memory in which an activate command with said row index is sent to said memory, wherein an overhead of said performing the iterative block cipher operation is hidden within said time period.
2 . The encryption circuit of claim 1 , wherein the encryption circuit further comprises:
a data encryption/decryption circuit responsive to said encrypted counter value for encrypting a data element of a memory access using said encrypted counter value,
wherein the encryption circuit uses said data encryption/decryption circuit during a column operation to said memory.
3 . The encryption circuit of claim 2 , wherein said data encryption/decryption circuit comprises:
a plurality of exclusive-OR gates having first inputs for receiving a corresponding bit of said encrypted counter value, a second input for receiving a data value, and an output for providing a modified data value,
wherein during an encryption operation, said data value is plaintext and said modified data value is encrypted, and during a decryption operation, said data value is encrypted and said modified data value is plaintext.
4 . The encryption circuit of claim 1 , further comprising:
an adjustment circuit for adjusting said encrypted counter value to another width according to a deterministic algorithm, wherein the other width is a width of data of a data access during a column access command.
5 . The encryption circuit of claim 1 , wherein said iterative block cipher circuit uses said secret key and a key fragment provided by one of a host processor and an associated processor-in-memory to generate a second key, and uses said second key to perform said block cipher process.
6 . A data processing system comprising:
a host processor;
a memory coupled to said host processor;
a processor-in-memory coupled to said memory,
wherein each of said host processor and said processor-in-memory comprises an encryption circuit comprising:
an iterative block cipher circuit having a counter input for receiving a row index, a key input for receiving a secret key, and an output for providing an encrypted counter value in response to performing a block cipher process using said row index as a counter and said secret key; and
wherein said encryption circuit uses said iterative block cipher circuit to perform an iterative block cipher operation during a time period of a row activation operation to said memory in which said host processor sends an activate command with said row index to said memory, wherein an overhead of said performing the iterative block cipher operation is hidden within said time period.
7 . The data processing system of claim 6 , wherein the encryption circuit further comprises:
a data encryption/decryption circuit responsive to said encrypted counter value for encrypting a data element of a memory access using said encrypted counter value,
wherein the encryption circuit uses said data encryption/decryption circuit during a column operation to said memory.
8 . The data processing system of claim 7 , wherein said data encryption/decryption circuit comprises:
a plurality of exclusive-OR gates having first inputs for receiving a corresponding bit of said encrypted counter value, a second input for receiving a data value, and an output for providing a modified data value,
wherein during an encryption operation, said data value is plaintext and said modified data value is encrypted, and during a decryption operation, said data value is encrypted and said modified data value is plaintext.
9 . The data processing system of claim 6 , further comprising:
an adjustment circuit for adjusting said encrypted counter value to another width according to a deterministic algorithm, wherein the other width is a width of data of a data access during a column access command.
10 . The data processing system of claim 6 , wherein said encryption circuit is part of the host processor and the host processor further comprises:
an address decoder circuit having an input for receiving an address of a memory access, and an output for providing said row index, said address decoder circuit generating said row index from a row address portion of said address of said memory access using configuration information.
11 . The data processing system of claim 10 , wherein said address decoder circuit comprises:
a memory configuration decoder having an input for receiving said address of said memory access, and an output for providing a preliminary row index; and
a deterministic function circuit having an input coupled to said output of said memory configuration decoder, and an output for providing said row index.
12 . The data processing system of claim 6 , wherein said iterative block cipher circuit uses said secret key and a key fragment provided by one of said host processor and said processor-in-memory to generate a second key, and uses said second key to perform said block cipher process.
13 . A method for securely storing data in a memory, comprising:
generating a memory access request;
responsive to determining that a memory row of said memory access request is not open:
opening said memory row in the memory during a row activation operation, wherein said opening comprises sending an activate command with a row index to the memory; and
generating, during a time period of said row activation operation, an encrypted counter value based on using said row index of said memory row as a counter and a secret key, wherein an overhead of said generating the encrypted counter value is hidden within said time period;
thereafter:
encrypting data of said memory access request using said encrypted counter value responsive to determining that said memory access request is a write command; and
decrypting data of said memory access request using said encrypted counter value responsive to determining that said memory access request is a read command.
14 . The method of claim 13 , wherein said generating said encrypted counter value comprises:
generating said encrypted counter value using an iterative algorithm performed over a plurality of clock cycles.
15 . The method of claim 13 , generating said encrypted counter value further comprises:
using an iterative block cipher in counter mode.
16 . The method of claim 15 , wherein said using said iterative block cipher in said counter mode comprises:
forming an initial counter value in response to said row index; and
generating said encrypted counter value using said secret key in response to said forming.
17 . The method of claim 16 , wherein said forming comprises:
forming said initial counter value in response to said row index modified by a deterministic logic function.
18 . The method of claim 13 , wherein said encrypting said data comprises:
changing said data to encrypted data by performing a bit-by-bit exclusive-OR operation on bits of data with corresponding bits of said encrypted counter value.
19 . The method of claim 13 , wherein said generating said encrypted counter value comprises:
adjusting said encrypted counter value to another width according to a deterministic algorithm.