Processing system, integrated circuit, device, and method for data transfer for secure processing

1 . A processing system comprising:

a non-secure processing unit; and

a cryptographic coprocessing unit comprising:

a data interface configured to receive, from the non-secure processing unit, one or more control blocks and one or more data blocks; and

a hardware cryptographic engine configured to process, as a function of a cryptographic key, the one or more control blocks and the one or more data blocks received by the data interface;

wherein the data interface is configured to receive a first control block from the non-secure processing unit;

wherein the data interface is configured to latch the received first control block;

wherein the data interface is configured to receive a first data block from the non-secure processing unit; and

wherein the data interface is configured to transfer the latched first control block and the received first data block to the hardware cryptographic engine;

wherein the first control block contains a counter set value corresponding to a number of data blocks to be received by the data interface from the non-secure processing unit without a corresponding control block;

wherein the data interface is configured to set a countdown counter to the counter set value in the first control block; and

wherein the data interface is configured to decrement the countdown counter by one for each data block received from the non-secure processing unit without a corresponding control block.

2 . The processing system of claim 1 , wherein the data interface is configured to receive a second data block from the non-secure processing unit; and

wherein, if the second data block is received from the non-secure processing unit without a corresponding second control block, the data interface is configured to transfer the latched first control block and the received second data block to the hardware cryptographic engine.

3 . The processing system of claim 2 , wherein the data interface is configured to receive a second control block from the non-secure processing unit;

wherein the data interface is configured to latch the received second control block;

wherein the data interface is configured to receive a third data block from the non-secure processing unit; and

wherein the data interface is configured to transfer the latched second control block and the received third data block to the hardware cryptographic engine.

4 . The processing system of claim 3 , wherein the data interface is configured to receive a fourth data block from the non-secure processing unit; and

wherein, if the fourth data block is received from the non-secure processing unit without a corresponding third control block, the data interface is configured to transfer the latched second control block and the received fourth data block to the hardware cryptographic engine.

5 . The processing system of claim 1 , wherein, after each data block received by the data interface from the non-secure processing unit without a corresponding control block, the data interface is configured to check a current value of the countdown counter; and

wherein, if the current value of the countdown counter equals zero, the data interface is configured to expect to receive a control block with a next data block received from the non-secure processing unit.

6 . The processing system of claim 1 , wherein the hardware cryptographic engine is configured to support an Advanced Encryption Standard operation.

7 . The processing system of claim 1 , wherein each of the one or more control blocks contains eight bytes of data and each of the one or more data blocks contains sixteen bytes of data.

8 . A processing system comprising:

a non-secure processing unit; and

a cryptographic coprocessing unit comprising:

a data interface configured to receive, from the non-secure processing unit, a plurality of control blocks and a plurality of data blocks, at least some of the plurality of data blocks received subsequent to corresponding respective ones of the plurality of control blocks; and

a hardware cryptographic engine configured to process, as a function of a cryptographic key, the plurality of control blocks and the plurality of data blocks received by the data interface;

wherein the data interface is configured to latch each control block as each control block is received, overwriting any previously latched control block; and

wherein, each time a data block is received, the data interface is configured to transfer the latched control block and the received data block to the hardware cryptographic engine;

wherein at least a first one of the plurality of control blocks contains a counter set value corresponding to a number of data blocks to be received by the data interface from the non-secure processing unit without a corresponding control block;

wherein the data interface is configured to set a countdown counter to the counter set value in the first one of the plurality of control blocks; and

wherein the data interface is configured to decrement the countdown counter by one for each data block received from the non-secure processing unit without a corresponding control block.

9 . The processing system of claim 8 , wherein, after each data block received by the data interface from the non-secure processing unit without a corresponding control block, the data interface is configured to check a current value of the countdown counter; and

wherein, if the current value of the countdown counter equals zero, the data interface is configured to expect to receive a control block with a next data block received from the non-secure processing unit.

10 . The processing system of claim 8 , wherein the hardware cryptographic engine is configured to support an Advanced Encryption Standard operation.

11 . The processing system of claim 8 , wherein each of the plurality of control blocks contains eight bytes of data and each of the plurality of data blocks contains sixteen bytes of data.

12 . A method for receiving data to be cryptographically processed, the method comprising:

receiving, by a data interface of a cryptographic coprocessing unit from a non-secure processing unit, a first control block;

latching, by the data interface from the non-secure processing unit, the received first control block;

receiving, by the data interface from the non-secure processing unit, a first data block, the first control block containing a counter set value corresponding to a number of data blocks to be received by the data interface from the non-secure processing unit without a corresponding control block;

transferring, by the data interface to a hardware cryptographic engine of the cryptographic coprocessing unit, the latched first control block and the received first data block;

setting, by the data interface of the cryptographic coprocessing unit, a countdown counter to the counter set value in the first control block; and

decrementing, by the data interface of the cryptographic coprocessing unit, the countdown counter by one for each data block received from the non-secure processing unit without a corresponding control block.

13 . The method of claim 12 , further comprising:

receiving, by the data interface from the non-secure processing unit, a second data block; and

if the second data block is received from the non-secure processing unit without a corresponding second control block, transferring, by the data interface to the hardware cryptographic engine of the cryptographic coprocessing unit, the latched first control block and the received second data block.

14 . The method of claim 12 , further comprising:

after each data block without a corresponding control block is received by the data interface from the non-secure processing unit, checking, by the data interface, a current value of the countdown counter;

wherein, if the current value of the countdown counter equals zero, the data interface is configured to expect to receive a control block with a next data block received from the non-secure processing unit.

15 . The method of claim 12 , further comprising:

receiving, by the data interface from the non-secure processing unit, a second control block;

latching, by the data interface of the cryptographic coprocessing unit, the received second control block;

receiving, by the data interface from the non-secure processing unit, a third data block from the non-secure processing unit; and

transferring, by the data interface to the hardware cryptographic engine, the latched second control block and the received third data block.

16 . The method of claim 15 , further comprising:

receiving, by the data interface from the non-secure processing unit, a fourth data block; and

if the fourth data block is received from the non-secure processing unit without a corresponding third control block, transferring, by the data interface to the hardware cryptographic engine, the latched second control block and the received fourth data block.

17 . The method of claim 12 , wherein the hardware cryptographic engine is configured to support an Advanced Encryption Standard operation.