Deep learning-enabled synthesis of electromagnetic structures
Various embodiments comprise systems, methods, mechanisms, apparatus, and improvements thereof providing a machine learning based inverse design method for electromagnetic structures by specifying an electromagnetic structure design goal including a target electromagnetic response; representing a physical structure of an electromagnetic structure as an array of pixels, wherein each pixel indicates the presence or absence of conductive material wherein the represented physical structure of the electromagnetic structure further includes one or more input ports on one edge of the array and one output port on another edge of the array; providing a neural network (NN) based electromagnetic (EM) emulator configured to predict scattering parameters of electromagnetic structures represented by the array of pixels over frequencies of interest; and optimizing, using the NN-based EM emulator, across a multi-dimensional design space of possible electromagnetic structure representations using evolution algorithms until an electromagnetic structure substantially satisfying the electromagnetic structure design goal is reached.
1 . A method for designing an electromagnetic structure, comprising:
specifying an electromagnetic structure design goal including a target electromagnetic response;
representing a physical structure of an electromagnetic structure as an array of pixels, wherein each pixel indicates the presence or absence of conductive material, wherein the represented physical structure of the electromagnetic structure further includes one or more input ports on one edge of the array and one output port on another edge of the array;
providing a neural network (NN) based electromagnetic (EM) emulator configured to predict scattering parameters of electromagnetic structures represented by the array of pixels over frequencies of interest;
optimizing, using the NN-based EM emulator, across a multi-dimensional design space of possible electromagnetic structure representations using evolution algorithms until an electromagnetic structure substantially satisfying the electromagnetic structure design goal is reached.
2 . The method of claim 1 , further comprising realizing the physical structure of an optimized electromagnetic structure via on-chip metal layers.
3 . The method of claim 2 , wherein the realized physical structure of the optimized electromagnetic structure includes a DC pad at an edge for simultaneous transistor DC biasing and AC short at an edge.
4 . The method of claim 1 , wherein the electromagnetic structure design goal is associated with at least one of a two-port wideband output matching network, a two-port wideband inter-stage matching network, a two-port wideband input matching network, a three-port broadband in-phase power combiner/divider, and a three-port broadband Doherty combiner.
5 . The method of claim 1 , wherein the electromagnetic structure design goal is associated with an NN-port power combiner/divider, wherein NN is a integer greater than one.
6 . The method of claim 1 , wherein the CNN based EM emulator is trained in accordance with a training data set including scattering parameters of randomized pixelated structures over multiple frequencies for the type of represented electromagnetic structure.
7 . The method of claim 6 , wherein the CNN based EM emulator is designed by adjusting model parameters in a manner reducing test loss.
8 . The method of claim 7 , wherein the model parameter adjusting comprises adjusting a number of convolution layers and a number of fully connected layers.
9 . The method of claim 8 , wherein the convolution layers and fully connected layers both contain batch normalization and leaky rectified linear unit (ReLU) activation functions, the ReLU activation functions including dropout layers configured to avoid over-fitting.
10 . The method of claim 1 wherein the optimization uses a Genetic Algorithm (GA).
11 . The method of claim 10 , wherein the integrated PA circuit comprises a (NN−1)-way backoff efficient power combiner PA, comprising:
an inverse design optimized NN-port broadband backoff efficient combiner configured for optimum load modulation across frequency at (NN−1) input ports;
each of NN−1 branches comprising a respective optimized input electromagnetic structure for coupling a respective input signal to an input of a respective driver transistor array, and a respective optimized interstage electromagnetic structure disposed between an output of the respective driver transistor array and an input of a respective power transistor array.
12 . The method of claim 1 , wherein the electromagnetic structure comprises an impedance matching network used with active discrete or on-chip devices for power amplifier (PA) circuit synthesis.
13 . The method of claim 12 , further comprising realizing the physical structure of the optimized integrated PA circuit as a broadband low loss output matching network having an input port and an output port, the input port connected to a power delivery node of a power transistor array, and the output port connected to a driving port of a transmit antenna.
14 . The method of claim 13 , wherein the integrated PA circuit further comprises:
an optimized input impedance matching network disposed between an input signal port and an input of a driver transistor array; and
an optimized interstage impedance matching network disposed between an output of the driver transistor array and an input of a power transistor array.
15 . The method of claim 14 , wherein the power transistor array and driver transistor array are realized using integrated heterojunction bipolar transistors (HBTs).
16 . The method of claim 14 , wherein the interstage electromagnetic structure and input electromagnetic structure comprise at least one of a two-port wideband output matching network, a two-port wideband inter-stage matching network, a two-port wideband input matching network, a three-port broadband in-phase power combiner/divider, and a three-port broadband Doherty combiner.
17 . The method of claim 13 , wherein:
the interstage impedance matching network and input impedance matching network are realized using on-chip components comprising at least one of series microstrip lines, series on-chip Metal Insulator Metal (MIM) capacitors, microstrip open stubs, and DC feeding lines.
18 . The method of claim 17 , wherein the integrated PA circuit couples a broadband quadrature hybrid signal from an PA circuit input to a first port, and provides at first and second output ports carrier PA and peaking PA respectively.
19 . The method of claim 13 , wherein the integrated PA circuit comprises a 2-way power combining PA, integrated PA circuit further comprising:
a first branch comprising a first optimized input electromagnetic structure for coupling a first input signal to an input of a first driver transistor array, and a first optimized interstage electromagnetic structure disposed between an output of the first driver transistor array and an input of a first power transistor array; and
a second branch comprising a second optimized input electromagnetic structure for coupling a second input signal to an input of a second driver transistor array, and a second optimized interstage electromagnetic structure disposed between an output of the second driver transistor array and an input of a second power transistor array.
20 . The method of claim 19 , wherein the integrated PA circuit comprises a three-port wideband in-phase power combiner/divider.
21 . The method of claim 20 , wherein the integrated PA circuit comprises a 2-way Doherty PA, comprising an optimized three-port broadband Doherty combiner configured for optimum load modulation across frequency at two input ports.
22 . The method of claim 21 , wherein the integrated PA circuit comprises a class AB biased carrier PA and a class C adaptively biased peaking PA coupled to respective input ports of the Doherty combiner.
23 . A computer implemented method for designing an electromagnetic structure, comprising:
specifying an electromagnetic structure design goal including a target electromagnetic response;
specifying an electromagnetic structure design goal including a target electromagnetic response;
representing a physical structure of an electromagnetic structure as an array of pixels, wherein each pixel indicates the presence or absence of conductive material, wherein the represented physical structure of the electromagnetic structure further includes one or more input ports on one edge of the array and one output port on another edge of the array;
providing a neural network (NN) based electromagnetic (EM) emulator configured to predict scattering parameters of electromagnetic structures represented by the array of pixels over frequencies of interest;
optimizing, using the NN-based EM emulator, across a multi-dimensional design space of possible electromagnetic structure representations using evolution algorithms until an electromagnetic structure substantially satisfying the electromagnetic structure design goal is reached.