IP Library › Granted Patent US 12664341

Granted Patent B1

US 12664341 · App. 18/087,124 · Granted Jun 23, 2026

Performance and throughput when modeling half cycle paths during emulation or prototyping

Inventors: Alexander Rabinovitch (Shrewsbury, MA); Cedric Jean Alquier (Wissous, FR); Prashant Saxena (Portland, OR); Sivaprasad Acharaya (Singapore, SG)

Assignee: Synopsys, Inc.

G06F30/3308 G06F30/323

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Quick Facts

Patent No.: US 12664341
App. No.: 18/087,124
Granted: Jun 23, 2026
Kind: B1

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Abstract

A method of verifying a logic circuit design by a hardware emulation system, includes, in part, receiving a netlist of the logic circuit design configured to operate in response to positive edges of a first clock signal, and transforming each of a first multitude of flip-flops disposed in the logic circuit design to a dual-enable flip-flop configured to operate in response to positive edges of a second clock signal thereby to generate a transformed logic circuit design. The state of the logic circuit design after 2k cycles of the first clock is the same as a state of the transformed logic circuit design after k cycles of the second clock.

Claims (65)

1 . A method of verifying a logic circuit design by a hardware emulation system, the method comprising:

receiving a netlist of the logic circuit design configured to operate in response to positive edges of a first clock signal;

transforming each of a first plurality of flip-flops disposed in the logic circuit design to a dual-enable flip-flop configured to operate in response to positive edges of a second clock signal thereby to generate a transformed logic circuit design,

wherein a positive enable signal, a positive data input signal, and a positive data output signal of the dual-enable flip-flop respectively have similar values as an enable signal, data input signal and data output signal of the flip-flop during even cycles of the first clock,

wherein a negative enable signal, a negative data input signal, and a negative data output signal of the dual-enable flip-flop respectively have similar values as the enable signal, the data input signal and the data output signal of the flip-flop during odd cycles of the first clock, and

wherein a state of the logic circuit design after 2k cycles of the first clock is a same as a state of the transformed logic circuit design after k cycles of the second clock, wherein k is a positive integer.

2 . The method of claim 1 further comprising:

performing emulation of the transformed logic circuit design.

3 . The method of claim 1 further comprising:

generating a design clock signal from the first clock signal, wherein edges of the design clock signal change in response to positive edges of the first clock signal, and wherein the design clock is a fastest clock used in the logic circuit design.

4 . The method of claim 3 further comprising:

transforming each of a second plurality of flip-flips in the logic circuit design that is responsive to negative edges of the design clock into a first flip-flop and a first multiplexer, wherein the first flip-flop receives positive edges of the first clock and includes an enable terminal that is coupled to a select terminal of the first multiplexer, wherein a data input terminal of the first flip-flip is coupled to a first input terminal of the first multiplexer, and wherein a data output terminal of the first flip-flop is coupled to a second input terminal of the first multiplexer.

5 . The method of claim 1 wherein each dual-enable flip-flop comprises a flip-flop, a first multiplexer and a second multiplexer, wherein

a negative data input signal of the dual-enable flip-flop is applied to a first input terminal of the first multiplexer, a negative enable terminal of the dual-enable flip-flop is applied to a select terminal of the first multiplexer, and an output of the first multiplexer is applied to a data input terminal of the flip-flop,

a positive data input signal of the dual-enable flip-flop is applied to a first input terminal of the second multiplexer, and a positive enable terminal of the dual-enable flip-flop is applied to a select terminal of the second multiplexer,

an output of the second multiplexer supplies the positive output signal of the dual-enable flip-flop, and

an output of the flip-flop supplies the negative output signal of the dual-enable flip-flop.

6 . The method of claim 1 wherein a positive data output signal of a first one of the plurality of dual-enable flip-flops is received as a negative data signal by a second one of the plurality of dual-enable flip-flops, and a negative data output signal of the first one of the plurality of dual-enable flip-flops is received as a positive data signal by the second one of the plurality of dual-enable flip-flops.

7 . The method of claim 6 wherein a positive data output signal of a third one of the plurality of dual-enable flip-flops is received as positive enable signals of the first and second ones of the plurality of dual flip-flops, and a negative data output signal of the third one of the plurality of dual-enable flip-flops is received as negative enable signals of the first and second ones of the plurality of dual flip-flops.

8 . The method of claim 2 further comprising:

pausing the emulation in response to a request to make a function call triggered by the design clock;

computing a first function, responsive to a positive edge of the design clock, by a computer system that is in communication with the hardware emulation system;

computing a second function, responsive to a negative edge of the design clock, by the computer system while the emulation remains paused; and

resuming the emulation after results of the first and second functions are computed and returned to the hardware emulation system.

9 . The method of claim 1 further comprising:

replicating a first combinatorial gate disposed between an output of a first one of the plurality of dual-enable flip-flops and inputs of a second one of the plurality of dual-enable flip-flops and a third one of the plurality of dual-enable flip-flops if the first one of the plurality of dual-enable flip-flops has a non-zero negative enable signal, the second one of the plurality of dual-enable flip-flops has a non-zero negative enable signal during negative cycles of the design clock, and the third one of the plurality of dual-enable flip-flops has a non-zero positive enable signal during positive cycles of the design clock.

10 . The method of claim 3 further comprising:

identifying, from among a plurality of clock signals derived from the design clock, at least a first clock signal having a frequency that is smaller than a frequency of the design clock; and

shifting times of changes of the first clock such that each time shifted change occurs at substantially a same time as a nearest upcoming rising of edge of the design clock.

11 . A hardware emulation system comprising:

a memory storing instructions; and

a processor, coupled with the memory and configured to execute the instructions, the instructions when executed causing the processor to:

receive a netlist of the logic circuit design configured to operate in response to positive edges of a first clock signal; and

transform each of a first plurality of flip-flops disposed in the logic circuit design to a dual-enable flip-flop configured to operate in response to positive edges of a second clock signal thereby to generate a transformed logic circuit design,

12 . The hardware emulation system of claim 11 wherein the instructions further cause the processor to:

perform emulation of the transformed logic circuit design.

13 . The hardware emulation system of claim 11 , wherein the instructions further cause the processor to:

generate a design clock signal from the first clock signal, wherein edges of the design clock signal change in response to positive edges of the first clock signal, and wherein the design clock is a fastest clock used in the logic circuit design.

14 . The hardware emulation system of claim 13 , wherein the instructions further cause the processor to:

transform each of a second plurality of flip-flip in the logic circuit design that is responsive to negative edges of the design clock into a first flip-flop and a first multiplexer, wherein the first flip-flop receives positive edges of the first clock and includes an enable terminal that is coupled to a select terminal of the first multiplexer, wherein a data input terminal of the first flip-flip is coupled to a first input terminal of the first multiplexer, and wherein a data output terminal of the first flip-flop is coupled to a second input terminal of the first multiplexer.

15 . The hardware emulation system of claim 11 , wherein each dual-enable flip-flop comprises a flip-flop, a first multiplexer and a second multiplexer, wherein

an output of the second multiplexer supplies the positive output signal of the dual-enable flip-flop, and

an output of the flip-flop supplies the negative output signal of the dual-enable flip-flop.

16 . The hardware emulation system of claim 11 , wherein a positive data output signal of a first one of the plurality of dual-enable flip-flops is received as a negative data signal by a second one of the plurality of dual-enable flip-flops, and a negative data output signal of the first one of the plurality of dual-enable flip-flops is received as a positive data signal by the second one of the plurality of dual-enable flip-flops.

17 . The hardware emulation system of claim 12 wherein the instructions further cause the processor to:

pause the emulation in response to a request to make a function call triggered by the design clock;

compute a first function, responsive to a positive edge of the design clock, by a computer system that is in communications with the hardware emulation system;

compute a second function, responsive to a negative edge of the design clock, by the computer system while the emulation remains paused; and

resume the emulation after results of the first and second functions are computed and returned to the hardware emulation system.

18 . The hardware emulation system of claim 11 wherein the instructions further cause the processor to:

replicate a first combinatorial gate disposed between an output of a first one of the plurality of dual-enable flip-flops and inputs of a second one of the plurality of dual-enable flip-flops and a third one of the plurality of dual-enable flip-flops if the first one of the plurality of dual-enable flip-flops has a non-zero negative enable signal, the second one of the plurality of dual-enable flip-flops has a non-zero negative enable signal during negative cycles of the design clock, and the third one of the plurality of dual-enable flip-flops has a non-zero positive enable signal during positive cycles of the design clock.

19 . The hardware emulation system of claim 13 wherein the instructions further cause the processor to:

identify, from among a plurality of clock signals derived from the design clock, at least a first clock signal having a frequency that is at least twice smaller than a frequency of the design clock; and

shift times of changes of the first clock such that each time shifted change occurs at substantially a same time as a nearest upcoming rising of edge of the design clock.

20 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

receive a netlist of the logic circuit design configured to operate in response to positive edges of a first clock signal; and