Structure including passive component traversing multiple semiconductor chips, with related methods and systems
Embodiments of the disclosure provide a structure including a passive component traversing multiple semiconductor chips, with related systems and methods. A structure of the disclosure includes a plurality of stacked semiconductor chips including a first chip coupled to a second chip through an interface. A passive component traverses the interface between the first chip and the second chip of the plurality of stacked semiconductor chips. The passive component includes a first portion within the first chip and a second portion within the second chip.
1 . A structure comprising:
a plurality of stacked semiconductor chips including a first chip coupled to a second chip through an interface; and
a passive component traversing the interface between the first chip and the second chip of the plurality of stacked semiconductor chips, wherein the passive component includes:
a first portion within the first chip and a second portion within the second chip, and
a set of ports coupling a set of conductors in the first chip to the passive component, wherein the set of ports is free of couplings to the second chip.
2 . The structure of claim 1 , further comprising an alignment marker for the passive component within the first chip, wherein the second chip does not include a corresponding alignment marker.
3 . The structure of claim 1 , wherein the passive component includes at least one of an inductor, a transformer, a waveguide, a capacitor, a resistor, or a memory cell.
4 . The structure of claim 1 , wherein the passive component includes at least one back end of line (BEOL) component.
5 . A method comprising:
generating a three-dimensional model of a passive component traversing a plurality of stacked semiconductor chips, wherein the three-dimensional model includes:
a first portion of the passive component in a first chip, the first portion including all ports for the passive component and being configured to simulate electrical operation of the passive component as part of the first chip, and
a second portion of the passive component in a second chip, wherein the second portion does not include any ports for the passive component; and
fabricating the passive component based on the three-dimensional model.
6 . The method of claim 5 , wherein the first portion includes an alignment marker for the passive component wherein the second portion does not include a corresponding alignment marker.
7 . The method of claim 6 , further comprising changing a location of the alignment marker within the first portion based on whether the alignment marker violates a design rule for the first portion and the second portion in the three-dimensional model.
8 . The method of claim 5 , wherein the passive component includes at least one back end of line (BEOL) component.
9 . The method of claim 5 , wherein the passive component includes at least one of an inductor, a transformer, a waveguide, a capacitor, a resistor, or a memory cell.
10 . The method of claim 5 , wherein fabricating the passive component includes:
fabricating the first chip and the second chip based on the three-dimensional model; and
joining the first chip to the second chip based on the three-dimensional model.
11 . The method of claim 10 , wherein fabricating the passive component further includes:
fabricating a first portion of the passive component within the first chip; and
fabricating a second portion of the passive component within the second chip.
12 . The method of claim 5 , further comprising:
simulating an operation of the passive component solely based on the first portion; and
fabricating the passive component based on the simulated operation of the passive component.
13 . The method of claim 12 , further comprising modifying one of the first portion or the second portion of the three-dimensional model based on the simulated operation, wherein fabricating the passive component is based on the modified one of the first portion or the second portion.
14 . A system comprising:
a computing device configured to generate a three-dimensional model of a passive component traversing a plurality of stacked semiconductor chips, wherein the three-dimensional model includes:
a first portion of the passive component in a first chip, the first portion including all ports for the passive component and being configured to simulate electrical operation of the passive component as part of the first chip, and
a second portion of the passive component in a second chip, wherein the second portion does not include any ports for the passive component; and
a manufacturing device in communication with the computing device and configured to fabricate the passive component based on the three-dimensional model.
15 . The system of claim 14 , wherein the computing device is further configured to simulate an operation of the passive component solely based on the first portion, and wherein the manufacturing device is further configured to fabricate the passive component based on the simulated operation of the passive component.
16 . The system of claim 15 , wherein the computing device is further configured to reposition an alignment marker for the passive component based on whether the alignment marker within the first portion of the three-dimensional model violates a design rule for the first portion or the second portion of the three-dimensional model.
17 . The system of claim 15 , wherein the computing device is further configured to modify to one of the first portion or the second portion of the three-dimensional model based on the simulated operation, wherein fabricating the passive component is based on the modified one of the first portion or the second portion.
18 . The system of claim 14 , wherein the passive component includes at least one back end of line (BEOL) component.
19 . The system of claim 14 , wherein the passive component includes at least one of an inductor, a transformer, a waveguide, a capacitor, a resistor, or a memory cell.
20 . The system of claim 14 , wherein the manufacturing device is further configured to fabricate an alignment marker for the passive component within the first chip, wherein the second chip does not include a corresponding alignment marker.