System, method, and computer program product for automatic partitioning of large and complex analog/mixed signal electronic designs
The present disclosure relates to a computer-implemented method for automatically partitioning an electronic design. Embodiments may include accessing, using the at least one processor, the electronic design and partitioning the electronic design using a multi-mode partitioning methodology. Embodiments may further include defining a cost function that determines a score for one or more partitioned sections of the electronic design from a plurality of partitioning methodologies and performing a routing operation on a first partitioned section and a second partitioned section from the one or more partitioned sections concurrently.
1 . A computer-implemented method for automatically partitioning an electronic design comprising:
accessing, using at least one processor, the electronic design;
partitioning the electronic design using a multi-mode partitioning methodology, wherein the multi-mode partitioning methodology includes feature-based partitioning and cluster-based partitioning, and wherein the feature-based partitioning includes two or more of width spacing pattern based partitioning, row-region based partitioning, virtual groups based partitioning, modgen-based partitioning, and automatic grouping;
defining a cost function that determines a score for one or more partitioned sections of the electronic design from a plurality of partitioning methodologies; and
performing a routing operation on a first partitioned section and a second partitioned section from the one or more partitioned sections concurrently.
2 . The computer-implemented method for electronic design of claim 1 , wherein the multi-mode partitioning methodology includes feature-based partitioning.
3 . The computer-implemented method for electronic design of claim 1 , wherein the multi-mode partitioning methodology includes cluster-based partitioning.
4 . The computer-implemented method for electronic design of claim 1 , wherein the cost function is based upon, at least in part, a number of spines associated with the electronic design.
5 . The computer-implemented method for electronic design of claim 4 , further comprising:
identifying a most optimal partitioning approach based upon, at least in part, an output of the cost function.
6 . A non-transitory computer-readable storage medium having stored thereon instructions, which when executed by a processor result in one of more operations for electronic design, the operations comprising:
accessing, using the at least one processor, the electronic design;
partitioning the electronic design using a multi-mode partitioning methodology, wherein the multi-mode partitioning methodology includes feature-based partitioning and cluster-based partitioning, and wherein the feature-based partitioning includes two or more of width spacing pattern based partitioning, row-region based partitioning, virtual groups based partitioning, modgen-based partitioning, and automatic grouping;
defining a cost function that determines a score for one or more partitioned sections of the electronic design from a plurality of partitioning methodologies; and
performing a routing operation on a first partitioned section and a second partitioned section from the one or more partitioned sections concurrently.
7 . The non-transitory computer-readable storage medium of claim 6 , wherein the multi-mode partitioning methodology includes feature-based partitioning.
8 . The non-transitory computer-readable storage medium of claim 6 , wherein the multi-mode partitioning methodology includes cluster-based partitioning.
9 . The non-transitory computer-readable storage medium of claim 6 , wherein the cost function is based upon, at least in part, a number of spines associated with the electronic design.
10 . The non-transitory computer-readable storage medium of claim 9 , further comprising:
identifying a most optimal partitioning approach based upon, at least in part, an output of the cost function.
11 . An electronic design system comprising:
at least one processor configured to access, using the at least one processor, the electronic design, the at least one processor further configured to partition the electronic design using a multi-mode partitioning methodology, wherein the multi-mode partitioning methodology includes feature-based partitioning and cluster-based partitioning, and wherein the feature-based partitioning includes two or more of width spacing pattern based partitioning, row-region based partitioning, virtual groups based partitioning, modgen-based partitioning, and automatic grouping, the at least one processor further configured to define a cost function that determines a score for one or more partitioned sections of the electronic design from a plurality of partitioning methodologies, the at least one processor further configured to perform a routing operation on a first partitioned section and a second partitioned section from the one or more partitioned sections concurrently.
12 . The electronic design system of claim 11 , wherein the multi-mode partitioning methodology includes feature-based partitioning.
13 . The electronic design system of claim 11 , wherein the multi-mode partitioning methodology includes cluster-based partitioning.
14 . The electronic design system of claim 11 , wherein the cost function is based upon, at least in part, a number of spines associated with the electronic design.