Integrated circuit device and manufacturing method of the same

1 . A method, comprising:

obtaining, by a processor, information on gate pitch and a ratio between the gate pitch and a first metal line pitch;

comparing, by the processor, a preset metal line end spacing with a second metal line pitch, of a plurality of metal traces, and a spacing between a metal line layer and a power rail layer;

in response to the comparison, defining, by the processor, a plurality of first metal line patterns, overlapping a plurality of first gate patterns, for formation by a first mask and defining a plurality of second metal line patterns, disposed between two adjacent gate patterns in a plurality of second gate patterns, for formation by a second mask;

placing, by the processor, the plurality of first metal line patterns in a first row in a floorplan of an integrated circuit layout design and the plurality of second metal line patterns in a second row, adjacent the first row; and

manufacturing, by at least one fabrication tool, at least one element in an integrated circuit based on the integrated circuit layout design, wherein manufacturing, by the at least one fabrication tool, the at least one element comprises:

forming in a same metal layer, by a first mask and a second mask for the same metal layer, a plurality of first metal lines corresponding to the plurality of first metal line patterns and a plurality of second metal lines corresponding to the plurality of second metal line patterns, respectively.

2 . The method of claim 1 , wherein the ratio between the gate pitch and the first metal line pitch is 1:1 or 2:1.

3 . The method of claim 1 , wherein one of the plurality of second metal line patterns overlaps a conductive segment pattern and corresponds to an output terminal of a logic circuit cell.

4 . The method of claim 3 , wherein lengths of the plurality of first metal line patterns and the plurality of second metal line patterns are less than 1.1 times of a cell height of the logic circuit cell.

5 . The method of claim 1 , wherein defining, by the processor, the plurality of first metal line patterns comprises:

defining a first line of the plurality of first metal line patterns having a first length larger than a row height of the first row;

wherein placing the plurality of first metal line patterns in the first row comprises:

placing an end of the first line in the plurality of first metal line patterns apart from a boundary of the second row by a distance at least larger than or equal to a first line end spacing.

6 . The method of claim 5 , wherein defining, by the processor, the plurality of second metal line patterns comprises:

defining a first line of the plurality of second metal line patterns having a second larger than a row height of the second row;

wherein placing the plurality of second metal line patterns in the second row comprises:

placing an end of the first line of the plurality of second metal line patterns apart from a first boundary of the first row by a distance at least larger than or equal to a second line end spacing while a second boundary of the first row passes across the first line of the plurality of second metal line patterns.

7 . The method of claim 6 , wherein the first and second line end spacings are different from each other.

8 . The method of claim 1 , further comprising:

defining, by the processor, a third metal line pattern with respect to the plurality of second metal line patterns; and

placing the third metal line patterns in the first row, wherein the plurality of first metal line patterns, the plurality of second metal line patterns, the third metal line pattern, the plurality of first gate patterns, and the plurality of second gate patterns extend in a same direction.

9 . The method of claim 8 , further comprising:

defining, by the processor, a fourth metal line pattern configured with respect to the plurality of second metal line patterns; and

placing, by the processor, the fourth metal line pattern, having a length M 1 LB, in a third row, wherein the first to third rows, having a row height RH, interlaced with each other and the first row is interposed between the second and third rows, wherein a first line of the plurality of second metal line pattern and the third to fourth metal line patterns are placed within a same gate pitch,

wherein the row height RH satisfies mathematical relationship (1) and (2):

3× RH> 3× M 1 LB+ 4× EE   (1)

RH+P _ M 0+ S _ M 0≥ M 1 LB+ 2× EE   (2)

wherein EE corresponds to a line end spacing, between the third to fourth metal line patterns, equal to a line end spacing between the third metal line pattern and the first line of the plurality of second metal line patterns, P_M 0 corresponds to the second metal line pitch of the plurality of metal traces placed in a layer below the first line of the plurality of second metal line patterns and the third to fourth metal line patterns, and S_M 0 corresponds to a spacing between two adjacent traces in the plurality of metal traces.

10 . A method, comprising:

obtaining, by the processor, information on gate pitch, a ratio between the gate pitch and a metal line pitch, and a set of design rules of a layout design;

creating, by the processor, a floorplan having a plurality of first rows and a plurality of second rows that are interlaced with each other;

generating, by the processor, a first cell and a second cell that correspond to a first circuit and have a first cell height, comprising:

assigning a first line in a plurality of first metal line patterns, overlapping a plurality of gate patterns and for formation by a first mask, to the first cell; and

assigning a first line in a plurality of second metal line patterns, overlapping a plurality of conductive segment patterns and for formation by a second mask, to the second cell;

generating, by the processor, a third cell having a second cell height double the first cell height, comprising:

assigning a second line, having a length greater than the first cell height, in the plurality of first metal line patterns and a second line in the plurality of second metal line patterns to the third cell;

placing, by the processor, the first cell in a first row of the plurality of first rows and the second cell in a first row of the plurality of second rows, and placing, by the processor, the third cell in one of the plurality of first rows and a row, adjacent to the one of the plurality of first rows, of the plurality of second rows,

wherein the set of design rules of the layout design includes a first line end spacing between a boundary of the one in the plurality of second rows and an end of the second line in the plurality of first metal line patterns; and

manufacturing, by at least one fabrication tool, at least one element in an integrated circuit based on the layout design, wherein manufacturing, by the at least one fabrication tool, the at least one element comprises:

forming in a same metal layer, by a first mask and a second mask for the same metal layer, a plurality of first metal lines corresponding to the plurality of first metal line patterns and a plurality of second metal lines corresponding to the plurality of second metal line patterns, respectively.

11 . The method of claim 10 , wherein the second line in the plurality of first metal line patterns and the second line in the plurality of second metal line patterns correspond to internal metal lines or metal lines configured to receive signals for the first and second cells.

12 . The method of claim 11 , wherein the first cell height is smaller than about 110 nanometers, and the gate pitch is larger than about 44 nanometers.

13 . The method of claim 10 , wherein the set of design rules of the layout design further includes none of the plurality of first metal line patterns in the second cell and none of the plurality of second metal line patterns in the first cell.

14 . The method of claim 10 , wherein generating, by the processor, the first cell further comprises:

assigning a third line in the plurality of second metal line patterns to the first cell, wherein the third line in the plurality of second metal line patterns is coupled to a first line in a plurality of third metal line patterns in the first cell that are in a layer below the plurality of first metal line patterns and the plurality of second metal line patterns.

15 . The method of claim 10 , wherein the set of design rules of the layout design includes a second line end spacing between a boundary of the one in the plurality of first rows and an end of the second line in the plurality of second metal line patterns,

wherein the second line in the plurality of second metal line patterns extends from the one in the plurality of second rows to the one in the plurality of first rows.

16 . A method, comprising:

obtaining, by the processor, information for an integrated circuit layout design;

comparing by the processor, based on the information, a preset metal line end spacing with a first metal line pitch, of a plurality of metal traces, and a spacing between a metal line layer and a power rail layer;

in response to the comparison, defining, by the processor, a plurality of first metal line patterns, overlapping a plurality of first gate patterns, for formation by a first mask and defining, by the processor, a plurality of second metal line patterns, disposed between two adjacent gate patterns in a plurality of second gate patterns, for formation by a second mask;

placing, by the processor, the plurality of first metal line patterns in a first row in a floorplan of the integrated circuit layout design and the plurality of second metal line patterns in a second row; and

manufacturing, by at least one fabrication tool, at least one element in an integrated circuit based on the integrated circuit layout design, wherein manufacturing, by the at least one fabrication tool, the at least one element comprises:

forming in a same metal layer, by a first mask and a second mask for the same metal layer, a plurality of first metal lines corresponding to the plurality of first metal line patterns and a plurality of second metal lines corresponding to the plurality of second metal line patterns, respectively, wherein a first line of the plurality of first metal lines and a second line of plurality of second metal lines are staggered in two adjacent rows.

17 . The method of claim 16 , wherein defining, by the processor, the plurality of first metal line patterns comprises:

defining a first line of the plurality of first metal line patterns having a first length larger than a row height of the first row.

18 . The method of claim 17 , wherein placing, by the processor, the plurality of first metal line patterns in the first row comprises:

placing an end of the first line in the plurality of first metal line patterns apart from a boundary of the second row by a distance at least larger than or equal to a first line end spacing.

19 . The method of claim 15 , wherein the first and second line end spacings are different from each other.

20 . The method of claim 16 , wherein an end of the first line apart from a boundary of the second row by a first distance, and an end of the second line apart from a boundary of the first row by a second distance different from the first distance.