IP Library › Granted Patent US 12664391
Granted Patent B2
US 12664391 · App. 18/644,404 · Granted Jun 23, 2026

Energy harvesting with dual buffer capacitor arrangement

Inventor: Kevin Scott Buescher (Colorado Springs, CO)
Assignee: EM Microelectronic-Marin SA
G06K19/0726G06K19/0707G06K19/0715H02J50/001
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Quick Facts
Patent No.
US 12664391
App. No.
18/644,404
Granted
Jun 23, 2026
Kind
B2
Abstract

A system ( 10 ) including an energy harvesting circuit ( 12 ) connectable to an antenna ( 14 ) and configured to execute an autonomous matching procedure to match the antenna ( 14 ) to an electric load ( 15 ), a buffer capacitor ( 16 ) connected to the energy harvesting circuit ( 14 ) and chargeable by the energy harvesting circuit ( 14 ), and a control circuit ( 20 ) connected to the energy harvesting circuit ( 14 ) and to the buffer capacitor ( 16 ) and connectable to the electric load ( 15 ), wherein the control circuit ( 20 ) is configured to control a supply voltage of the electric load ( 15 ), and wherein the control circuit ( 20 ) comprises an auxiliary capacitor ( 22 ) chargeable during execution of the autonomous matching procedure.

Claims (52)

1 . A system ( 10 ) comprising:

an energy harvesting circuit ( 12 ) connectable to an antenna ( 14 ) and configured to execute an autonomous matching procedure to match the antenna ( 14 ) to an electric load ( 15 );

a buffer capacitor ( 16 ) connected to the energy harvesting circuit ( 14 ) and chargeable by the energy harvesting circuit ( 14 );

a control circuit ( 20 ) connected to the energy harvesting circuit ( 14 ) and to the buffer capacitor ( 16 ) and connectable to the electric load ( 15 ), wherein the control circuit ( 20 ) is configured to control a supply voltage of the electric load ( 15 ); and

wherein the control circuit ( 20 ) comprises an auxiliary capacitor ( 22 ) chargeable during execution of the autonomous matching procedure, and

the control circuit ( 20 ) comprises a voltage limiter ( 26 ) connected to an output of the energy harvesting circuit ( 14 ) and is configured to charge the auxiliary capacitor ( 22 ) by excess current provided by the voltage limiter ( 26 ) of the control circuit ( 20 ) during execution of the autonomous matching procedure.

2 . The system ( 10 ) according to claim 1 , wherein the control circuit ( 20 ) is either operable in an antenna matching mode or in a function mode and wherein the control circuit ( 20 ) is switchable from the antenna matching mode into the function mode upon or after completion of the autonomous matching procedure.

3 . The system ( 10 ) according to claim 2 , wherein the control circuit ( 20 ) comprises a switching arrangement ( 24 ) operable to switch the control circuit ( 20 ) between the antenna matching mode and the function mode.

4 . The system ( 10 ) according to claim 2 , wherein when the control circuit ( 20 ) is in the function mode, the auxiliary capacitor ( 22 ) is parallel to the buffer capacitor ( 16 ).

5 . The system ( 10 ) according to claim 1 , wherein the voltage limiter ( 26 ) is connected to the auxiliary capacitor ( 22 ) and is operable to charge the auxiliary capacitor ( 22 ) when the control circuit ( 20 ) is in an antenna matching mode.

6 . The system ( 10 ) according to claim 1 , wherein the voltage limiter ( 26 ) comprises a shunt limiter ( 27 ) operable to shunt excess current to ground.

7 . The system ( 10 ) according to claim 6 , wherein the auxiliary capacitor ( 22 ) is chargeable by excess current provided by the shunt limiter ( 27 ) when the control circuit ( 20 ) is in the antenna matching mode.

8 . The system ( 10 ) according to claim 6 , wherein the auxiliary capacitor ( 22 ) is exclusively chargeable by the excess current provided by the shunt limiter ( 27 ).

9 . The system ( 10 ) according to claim 1 , further comprising a current mirror ( 30 ) with a first branch ( 31 ) and a second branch ( 32 ), wherein the first branch ( 31 ) forms part of the voltage limiter ( 26 ) and wherein the auxiliary capacitor ( 22 ) is connected to or forms part of the second branch ( 32 ).

10 . The system ( 10 ) according to claim 3 , wherein the switching arrangement ( 24 ) comprises a PMOS transistor (PM 3 ) and an NMOS transistor (NM 3 ) and wherein a gate of the PMOS transistor (PM 3 ) is connected to a gate of the NMOS transistor (NM 3 ) and is connected to a switch input ( 34 ) providing a control signal being indicative of one of the antenna matching mode and the function mode.

11 . A passive RFID circuit comprising:

an antenna ( 14 );

an electric load ( 15 ); and

a system ( 10 ) according to claim 1 , wherein the energy harvesting circuit ( 12 ) is connected to the antenna ( 40 ) and wherein the electric load ( 15 ) is connected to the energy harvesting circuit ( 12 ) via the control circuit ( 20 ) and the buffer capacitor ( 16 ).

12 . A method of charging capacitors ( 16 , 22 ) of a system ( 10 ), wherein the system comprises:

an energy harvesting circuit ( 12 ) connectable to an antenna ( 14 ) and configured to execute an autonomous matching procedure to match the antenna ( 14 ) to an electric load ( 15 );

a buffer capacitor ( 16 ) connected to the energy harvesting circuit ( 14 );

a control circuit ( 20 ) connected to the energy harvesting circuit ( 14 );

an auxiliary capacitor ( 22 ) connectable to the energy harvesting circuit ( 14 ), the method comprising the steps of:

charging the buffer capacitor ( 16 );

executing the autonomous matching procedure; and

charging the auxiliary capacitor ( 22 ) during execution of the autonomous matching procedure,

wherein the auxiliary capacitor ( 22 ) is charged by excess current provided by a voltage limiter ( 26 ) of the control circuit ( 20 ) during execution of the autonomous matching procedure.

13 . The method according to claim 12 , wherein execution of the autonomous matching procedure is initiated when the buffer capacitor ( 16 ) has been charged to a first charge level by the energy harvesting circuit ( 12 ).

14 . A system ( 10 ) comprising:

an energy harvesting circuit ( 12 ) connectable to an antenna ( 14 ) and configured to execute an autonomous matching procedure to match the antenna ( 14 ) to an electric load ( 15 );

a buffer capacitor ( 16 ) connected to the energy harvesting circuit ( 14 ) and chargeable by the energy harvesting circuit ( 14 );

a control circuit ( 20 ) connected to the energy harvesting circuit ( 14 ) and to the buffer capacitor ( 16 ) and connectable to the electric load ( 15 ), wherein the control circuit ( 20 ) is configured to control a supply voltage of the electric load ( 15 ); and

wherein the control circuit ( 20 ) comprises an auxiliary capacitor ( 22 ) chargeable during execution of the autonomous matching procedure,

the control circuit ( 20 ) comprises a voltage limiter ( 26 ) connected to an output of the energy harvesting circuit ( 14 ), and

at least one of (A), (B), and (C) of which:

(A) comprises:

the voltage limiter ( 26 ) is connected to the auxiliary capacitor ( 22 ) and is operable to charge the auxiliary capacitor ( 22 ) when the control circuit ( 20 ) is in the antenna matching mode,

(B) comprises:

the voltage limiter ( 26 ) comprises a shunt limiter ( 27 ) operable to shunt excess current to ground, and

(C) comprises:

the control circuit ( 20 ) is either operable in an antenna matching mode or in a function mode and wherein the control circuit ( 20 ) is switchable from the antenna matching mode into the function mode upon or after completion of the autonomous matching procedure,

the control circuit ( 20 ) comprises a switching arrangement ( 24 ) operable to switch the control circuit ( 20 ) between the antenna matching mode and the function mode, and

the switching arrangement ( 24 ) comprises a PMOS transistor (PM 3 ) and an NMOS transistor (NM 3 ) and wherein a gate of the PMOS transistor (PM 3 ) is connected to a gate of the NMOS transistor (NM 3 ) and is connected to a switch input ( 34 ) providing a control signal being indicative of one of the antenna matching mode and the function mode.

15 . The system ( 10 ) according to claim 14 , wherein when the control circuit ( 20 ) is in the function mode, the auxiliary capacitor ( 22 ) is parallel to the buffer capacitor ( 16 ).

16 . The system ( 10 ) according to claim 14 , wherein the auxiliary capacitor ( 22 ) is chargeable by excess current provided by the shunt limiter ( 27 ) when the control circuit ( 20 ) is in the antenna matching mode.

17 . The system ( 10 ) according to claim 14 , wherein the auxiliary capacitor ( 22 ) is exclusively chargeable by the excess current provided by the shunt limiter ( 27 ).

18 . The system ( 10 ) according to claim 14 , further comprising a current mirror ( 30 ) with a first branch ( 31 ) and a second branch ( 32 ), wherein the first branch ( 31 ) forms part of the voltage limiter ( 26 ) and wherein the auxiliary capacitor ( 22 ) is connected to or forms part of the second branch ( 32 ).

19 . A passive RFID circuit comprising:

an antenna ( 14 ),

an electric load ( 15 ), and

a system ( 10 ) according to claim 16 , wherein the energy harvesting circuit ( 12 ) is connected to the antenna ( 40 ) and wherein the electric load ( 15 ) is connected to the energy harvesting circuit ( 12 ) via the control circuit ( 20 ) and the buffer capacitor ( 16 ).