Indirect chaining of command buffers
Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.
1 . An apparatus comprising:
a command processor comprising circuitry configured to:
access a data structure comprising a plurality of entries to be processed in a given order, wherein each of the plurality of entries comprises an address of a command buffer of a plurality of command buffers, distinct from the data structure, and at least two entries of the plurality of entries identify a same command buffer of the plurality of command buffers;
wherein addresses stored in the data structure are maintained until all of the plurality of entries have been processed.
2 . The apparatus as recited in claim 1 , wherein entries of the data structure define a chain of indirect buffers to be processed in the given order.
3 . The apparatus as recited in claim 2 , wherein a last entry in the chain comprises an indication that there are no further entries in the chain.
4 . The apparatus as recited in claim 1 , wherein each entry of the plurality of entries is configured to store an identification of a location external to the data structure.
5 . The apparatus as recited in claim 1 , wherein the command processor is configured to modify one or more data values consumed by at least one command buffer prior to reprocessing the at least one command buffer.
6 . The apparatus as recited in claim 1 , wherein each entry of the plurality of entries is configured to store an identification of a size of the entry and/or a location of a next entry in the data structure.
7 . The apparatus as recited in claim 1 , wherein the data structure corresponds to a received packet, and wherein at least one command buffer is configured to process a chain of command buffers using the data structure, responsive to determining the received packet includes a first indication.
8 . The apparatus as recited in claim 7 , wherein the at least one command buffer is configured to process a chain of command buffers without using the data structure, responsive to determining the received packet does not include the first indication.
9 . A method comprising:
accessing, by circuitry, a data structure comprising a plurality of entries to be processed in a given order, wherein each of the plurality of entries comprises an address of a command buffer of a plurality of command buffers, distinct from the data structure, and at least two entries of the plurality of entries identify a same command buffer of the plurality of command buffers;
wherein addresses stored in the data structure are maintained until all of the plurality of entries have been processed.
10 . The method as recited in claim 9 , wherein entries of the data structure define a chain of indirect buffers to be processed in the given order.
11 . The method as recited in claim 10 , wherein a last entry in the chain comprises an indication that there are no further entries in the chain.
12 . The method as recited in claim 9 , wherein each entry of the plurality of entries is configured to store an identification of a location external to the data structure.
13 . The method as recited in claim 9 , further comprising modifying one or more data values consumed by at least one command buffer prior to reprocessing the at least one command buffer.
14 . The method as recited in claim 9 , wherein each entry of the plurality of entries is configured to store an identification of a size of the entry and/or a location of a next entry in the data structure.
15 . The method as recited in claim 9 , wherein the data structure corresponds to a received packet, and the method further comprises processing a chain of command buffers using the data structure, responsive to determining the received packet includes a first indication.
16 . The method as recited in claim 15 , further comprising processing the chain of command buffers without using the data structure, responsive to determining the received packet does not include the first indication.
17 . A system comprising:
a first processor comprising circuitry configured to allocate storage for a data structure and a plurality of command buffers, distinct from the data structure, in a memory, the data structure comprising a plurality of entries to be processed in a given order, wherein each of the plurality of entries comprises an address of a command buffer of a plurality of command buffers, wherein at least two entries of the plurality of entries identify a same command buffer of the plurality of command buffers;
a second processor comprising circuitry configured to process the plurality of entries, wherein addresses stored in the data structure are maintained until all of the plurality of entries have been processed.
18 . The system as recited in claim 17 , wherein entries of the data structure define a chain of indirect buffers to be processed in the given order.
19 . The system as recited in claim 18 , wherein a last entry in the chain comprises an indication that there are no further entries in the chain.
20 . The system as recited in claim 17 , wherein each entry of the plurality of entries is configured to store an identification of a size of the entry and/or a location of a next entry in the data structure.