IP Library › Granted Patent US 12664932

Granted Patent B2

US 12664932 · App. 18/993,533 · Granted Jun 23, 2026

Trigger circuit and pixel driving circuit

Inventors: Jinyu Ren (Beijing, CN); Fangzhen Zhang (Beijing, CN); Xinxing Wang (Beijing, CN)

Assignee: BOE Technology Group Co., Ltd.

G09G3/32 G09G3/3233 G09G2300/0819 G09G2320/064

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Quick Facts

Patent No.: US 12664932
App. No.: 18/993,533
Granted: Jun 23, 2026
Kind: B2

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Abstract

A trigger circuit includes: an input sub-circuit, a reset sub-circuit, a control sub-circuit, a duty cycle adjustment sub-circuit and an output sub-circuit. The input sub-circuit controls a signal output terminal of the output sub-circuit to output a first power voltage or a second power voltage in response to an input control signal; the reset sub-circuit resets, in response to a reset signal, a first node through the reset signal, the first node being a connection node between the control sub-circuit and the duty cycle adjustment sub-circuit; the control sub-circuit controls a potential at the first node in response to a data voltage control signal; the duty cycle adjustment sub-circuit adjusts a duty cycle of a clock signal output from the signal output terminal in response to the potential at the first node, a potential of the clock signal jumps between the first power voltage and the second power voltage.

Claims (45)

1 . A trigger circuit, comprising: an input sub-circuit, a reset sub-circuit, a control sub-circuit, a duty cycle adjustment sub-circuit and an output sub-circuit, wherein

the input sub-circuit is configured to control a signal output terminal of the output sub-circuit to output a first power voltage or output a second power voltage in response to an input control signal;

the reset sub-circuit is configured to reset, in response to a reset signal, a first node through the reset signal, and the first node is a connection node between the control sub-circuit and the duty cycle adjustment sub-circuit;

the control sub-circuit is configured to control a potential at the first node in response to a data voltage control signal; and

the duty cycle adjustment sub-circuit is configured to adjust a duty cycle of a clock signal output from the signal output terminal of the output sub-circuit in response to the potential at the first node, and a potential of the clock signal jumps between the first power voltage and the second power voltage, and wherein

the input sub-circuit comprises a first transistor, a first electrode of the first transistor is connected with a second power voltage terminal, a second electrode of the first transistor is connected with the output sub-circuit, and a control electrode of the first transistor is connected with an input control signal terminal, and the reset sub-circuit comprises a second transistor, and a switching characteristic of the second transistor is opposite to a switching characteristic of the first transistor, wherein a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a control electrode of the second transistor and a reset signal terminal, or

the input sub-circuit comprises a first transistor, a first electrode of the first transistor is connected with a first power voltage terminal, a second electrode of the first transistor is connected with the output sub-circuit, and a control electrode of the first transistor is connected with an input control signal terminal, and the reset sub-circuit comprises a second transistor, and a switching characteristic of the second transistor is opposite to a switching characteristic of the first transistor, wherein a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a control electrode of the second transistor and a reset signal terminal.

2 . The trigger circuit of claim 1 , wherein the input sub-circuit comprises a first transistor, a first electrode of the first transistor is connected with a second power voltage terminal, a second electrode of the first transistor is connected with the output sub-circuit, and a control electrode of the first transistor is connected with an input control signal terminal, and the reset sub-circuit comprises a second transistor, and a switching characteristic of the second transistor is opposite to a switching characteristic of the first transistor, wherein a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a control electrode of the second transistor and a reset signal terminal, and wherein

the duty cycle adjustment sub-circuit comprises a third transistor, a first capacitor, and a second capacitor, and a switching characteristic of the third transistor is the same as a switching characteristic of the first transistor; and

a first electrode of the third transistor is connected with a first power voltage terminal, a second electrode of the third transistor is connected with the output sub-circuit and a first terminal of the first capacitor, a control electrode of the third transistor is connected with the first node and a first terminal of the second capacitor, and a second terminal of the first capacitor and a second terminal of the second capacitor are both connected with the second power voltage terminal.

3 . The trigger circuit of claim 2 , wherein the control sub-circuit comprises a fourth transistor and a fifth transistor, and a switching characteristic of the fourth transistor and a switching characteristic of the fifth transistor are both opposite to the switching characteristic of the third transistor;

a first electrode of the fourth transistor is connected with the first node, a second electrode of the fourth transistor is connected with a second electrode of the fifth transistor, and a control electrode of the fourth transistor is connected with the signal output terminal of the output sub-circuit; and

a first electrode of the fifth transistor is connected with the second power voltage terminal, and a control electrode of the fifth transistor is connected with a data voltage control terminal.

4 . The trigger circuit of claim 2 , wherein the control sub-circuit comprises a fifth transistor having a switching characteristic opposite to the switching characteristic of the third transistor; and

a first electrode of the fifth transistor is connected to the second power voltage terminal, a second electrode of the fifth transistor is connected to the first node, and a control electrode of the fifth transistor is connected to a data voltage control terminal.

5 . The trigger circuit of claim 1 , the input sub-circuit comprises a first transistor, a first electrode of the first transistor is connected with a first power voltage terminal, a second electrode of the first transistor is connected with the output sub-circuit, and a control electrode of the first transistor is connected with an input control signal terminal, and the reset sub-circuit comprises a second transistor, and a switching characteristic of the second transistor is opposite to a switching characteristic of the first transistor, wherein a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a control electrode of the second transistor and a reset signal terminal, and wherein

the duty cycle adjustment sub-circuit comprises a third transistor, a first capacitor, and a second capacitor, a switching characteristic of the third transistor is the same as the switching characteristic of the first transistor, a first electrode of the third transistor is connected with a second power voltage terminal, a second electrode of the third transistor is connected with the output sub-circuit and a first terminal of the first capacitor, a control electrode of the third transistor is connected with the first node and a first terminal of the second capacitor, and a second terminal of the first capacitor and a second terminal of the second capacitor are both connected with the first power voltage terminal.

6 . The trigger circuit of claim 5 , wherein the control sub-circuit comprises a fourth transistor and a fifth transistor, a switching characteristic of the fourth transistor is the same as the switching characteristic of the third transistor, and a switching characteristic of the fifth transistor is opposite to the switching characteristic of the third transistor;

a first electrode of the fifth transistor is connected with the first power voltage terminal, and a control electrode of the fifth transistor is connected with a data voltage control terminal.

7 . The trigger circuit of claim 5 , wherein the control sub-circuit comprises a fifth transistor having a switching characteristic opposite to the switching characteristic of the third transistor; and

a first electrode of the fifth transistor is connected to the first power voltage terminal, a second electrode of the fifth transistor is connected to the first node, and a control electrode of the fifth transistor is connected to a data voltage control terminal.

8 . The trigger circuit of claim 1 , wherein the output sub-circuit comprises a sixth transistor and a seventh transistor, and a switching characteristic of the sixth transistor is opposite to a switching characteristic of the seventh transistor;

a first electrode of the sixth transistor is connected with a first power voltage terminal, a second electrode of the sixth transistor is connected with the signal output terminal of the output sub-circuit, and a control electrode of the sixth transistor is connected with a control electrode of the seventh transistor, the input sub-circuit and the duty cycle adjustment sub-circuit; and

a first electrode of the seventh transistor is connected with a second power voltage terminal, and a second electrode of the seventh transistor is connected with the signal output terminal of the output sub-circuit.

9 . A pixel driving circuit, comprising a driving transistor and a trigger circuit, wherein a signal output terminal of the trigger circuit is connected with a control electrode of the driving transistor, and the trigger circuit comprises the trigger circuit of claim 1 .

10 . A trigger circuit, comprising: an input sub-circuit, a reset sub-circuit, a control sub-circuit and a duty cycle adjustment sub-circuit, wherein

the input sub-circuit is configured to control a signal output terminal to output a first power voltage or output a second power voltage in response to an input control signal, and the signal output terminal is a connection node between the input sub-circuit and the duty cycle adjustment sub-circuit;

the control sub-circuit is configured to control a potential at the first node in response to a data voltage control signal, an output signal of the signal output terminal, and the reset signal; and

the duty cycle adjustment sub-circuit is configured to adjust a duty cycle of a clock signal output from the signal output terminal in response to the potential at the first node, and a potential of the clock signal jumps between the first power voltage and the second power voltage, and wherein

the input sub-circuit comprises a first transistor, a first electrode of the first transistor is connected with a second power voltage terminal, a second electrode of the first transistor is connected with the signal output terminal, and a control electrode of the first transistor is connected with an input control signal terminal; the reset sub-circuit comprises a second transistor, and a switching characteristic of the second transistor is opposite to a switching characteristic of the first transistor, wherein a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a control electrode of the second transistor and a reset signal terminal, or

the input sub-circuit comprises a first transistor, a first electrode of the first transistor is connected with a first power voltage terminal, a second electrode of the first transistor is connected with the signal output terminal, and a control electrode of the first transistor is connected with an input control signal terminal; the reset sub-circuit comprises a second transistor, and a switching characteristic of the second transistor is opposite to a switching characteristic of the first transistor; and wherein a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a control electrode of the second transistor and a reset signal terminal.

11 . The trigger circuit of claim 10 , wherein the input sub-circuit comprises a first transistor, a first electrode of the first transistor is connected with a second power voltage terminal, a second electrode of the first transistor is connected with the signal output terminal, and a control electrode of the first transistor is connected with an input control signal terminal; the reset sub-circuit comprises a second transistor, and a switching characteristic of the second transistor is opposite to a switching characteristic of the first transistor, wherein a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a control electrode of the second transistor and a reset signal terminal, and wherein

the duty cycle adjustment sub-circuit comprises a third transistor, a first capacitor, and a second capacitor, a switching characteristic of the third transistor is the same as a switching characteristic of the first transistor, a first electrode of the third transistor is connected with a first power voltage terminal, a second electrode of the third transistor is connected with the signal output terminal and a first terminal of the first capacitor, a control electrode of the third transistor is connected with the first node and a first terminal of the second capacitor, and a second terminal of the first capacitor and a second terminal of the second capacitor are both connected with a second power voltage terminal.

12 . The trigger circuit of claim 11 , wherein the control sub-circuit comprises a fourth transistor, a fifth transistor, and a sixth transistor, a switching characteristic of the fourth transistor is the same as the switching characteristic of the third transistor, and a switching characteristic of the fifth transistor and a switching characteristic of the sixth transistor are both opposite to the switching characteristic of the third transistor;

a first electrode of the fourth transistor is connected with a second electrode of the fifth transistor and a first electrode of the sixth transistor, a second electrode of the fourth transistor is connected with the first node, and a control electrode of the fourth transistor is connected with a reset signal terminal;

a first electrode of the fifth transistor is connected with a second electrode of the sixth transistor and the second power voltage terminal, and a control electrode of the fifth transistor is connected with a data voltage control terminal; and

a control electrode of the sixth transistor is connected with the signal output terminal.

13 . The trigger circuit of claim 10 , wherein the input sub-circuit comprises a first transistor, a first electrode of the first transistor is connected with a first power voltage terminal, a second electrode of the first transistor is connected with the signal output terminal, and a control electrode of the first transistor is connected with an input control signal terminal; the reset sub-circuit comprises a second transistor, and a switching characteristic of the second transistor is opposite to a switching characteristic of the first transistor; and wherein a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a control electrode of the second transistor and a reset signal terminal, and wherein

the duty cycle adjustment sub-circuit comprises a third transistor, a first capacitor, and a second capacitor, a switching characteristic of the third transistor is the same as a switching characteristic of the first transistor, a first electrode of the third transistor is connected with a second power voltage terminal, a second electrode of the third transistor is connected with the signal output terminal and a first terminal of the first capacitor, a control electrode of the third transistor is connected with the first node and a first terminal of the second capacitor, and a second terminal of the first capacitor and a second terminal of the second capacitor are both connected with the first power voltage terminal.

14 . The trigger circuit of claim 13 , wherein the control sub-circuit comprises a fourth transistor, a fifth transistor, and a sixth transistor, a switching characteristic of the fourth transistor is the same as the switching characteristic of the third transistor, and a switching characteristic of the fifth transistor and a switching characteristic of the sixth transistor are both opposite to the switching characteristic of the third transistor;

a first electrode of the fifth transistor is connected with a second electrode of the sixth transistor and the first power voltage terminal, and a control electrode of the fifth transistor is connected with a data voltage control terminal; and

a control electrode of the sixth transistor is connected with the signal output terminal.