Scanning signal line drive circuit and display device provided with same
In a unit circuit constituting a shift register, as a constituent element for changing the potential of a node (first control node) connected to the gate terminal of an output control transistor from a high level to a low level, two thin film transistors (a first reset transistor and a second reset transistor) connected in series between the first control node and an input terminal for a low-level DC power supply voltage VSS are provided. A capacitor is provided between the drain terminal and the source terminal of each of the two thin film transistors.
1 . A scanning signal line drive circuit configured to drive a plurality of scanning signal lines disposed in a display portion of a display device, the scanning signal line drive circuit comprising:
a shift register including a plurality of unit circuits constituting a plurality of stages and respectively corresponding to the plurality of scanning signal lines, the shift register operating based on a plurality of clock signals cyclically corresponding to the plurality of unit circuits,
wherein each of the plurality of unit circuits includes
a first control node,
a second control node,
an output node connected to a corresponding scanning signal line,
an output control transistor including a control terminal connected to the first control node, a first conduction terminal to which an input clock signal, which is one of the plurality of clock signals, is supplied, and a second conduction terminal connected to the output node,
a set transistor including a control terminal to which a set signal is supplied, the set signal being an output signal output from a unit circuit of a z-th stage before a current stage, where z is a natural number, a first conduction terminal to which the set signal or an on level potential is supplied, and a second conduction terminal connected to the first control node,
a first reset transistor including a control terminal to which a first reset signal is supplied, the first reset signal being an output signal output from a unit circuit of an x-th stage after the current stage, where x is a natural number, a first conduction terminal connected to the first control node, and a second conduction terminal connected to the second control node,
a second reset transistor including a control terminal to which a second reset signal is supplied, the second reset signal being an output signal output from a unit circuit of a y-th stage after the current stage, where y is a natural number greater than the x, a first conduction terminal connected to the second control node, and a second conduction terminal to which an off level potential is supplied,
a first adjustment capacitor having one end connected to the first control node and the other end connected to the second control node, and
a second adjustment capacitor having one end connected to the second control node and the other end to which an off level potential is supplied, and
after the first reset transistor changes from an off state to an on state based on the first reset signal to change a potential of the first control node from an on level to an off level, the second reset transistor changes from an off state to an on state based on the second reset signal before the first reset transistor changes from the on state to the off state based on the first reset signal.
2 . The scanning signal line drive circuit according to claim 1 ,
wherein a relationship between the z, a number P of phases of the plurality of clock signals, and a duty ratio D of each of the plurality of clock signals satisfies the following expression,
z
/
P
≤
1
-
D
.
3 . The scanning signal line drive circuit according to claim 1 ,
wherein a relationship between the x, the y, the number P of phases of the plurality of clock signals, and the duty ratio D of each of the plurality of clock signals satisfies the following four expressions,
x
/
P
>
D
y
/
P
<
1
y
>
x
(
y
-
x
)
/
P
<
D
.
4 . The scanning signal line drive circuit according to claim 1 ,
wherein a relationship between the z, the x, the y, the number P of phases of the plurality of clock signals, and the duty ratio D of each of the plurality of clock signals satisfies the following five expressions,
z
/
P
≤
1
-
D
x
/
P
>
D
y
/
P
<
1
y
>
x
(
y
-
x
)
/
P
<
D
.
5 . The scanning signal line drive circuit according to claim 1 ,
wherein each of the plurality of unit circuits further includes a boost capacitor having one end connected to the first control node and the other end connected to the output node.
6 . The scanning signal line drive circuit according to claim 1 ,
wherein the first reset transistor and the second reset transistor are thin film transistors.
7 . The scanning signal line drive circuit according to claim 6 ,
wherein the first reset transistor and the second reset transistor each are a thin film transistor including a channel layer formed of an oxide semiconductor.
8 . A display device comprising:
a display portion in which a plurality of scanning signal lines are disposed; and
the scanning signal line drive circuit according to claim 1 .