Data processing device, data driving device and display device including the same
The embodiment discloses a data processing device, a data driving device, and a display device, wherein the data processing device transmits configuration data in a low-speed communication mode, transitions to a high-speed communication mode after the low-speed communication mode to transmit control data and image data, and retransmits a clock training pattern while maintaining the high-speed communication mode upon receiving a lock-fail signal during the operation of the high-speed communication mode.
1 . A data processing device, wherein the data processing device is configured to:
transmit configuration data in a low-speed communication mode;
transition to a high-speed communication mode after the low-speed communication mode and transmitting control data and image data;
retransmit a clock training pattern while maintaining the high-speed communication mode when a lock-fail signal is received during operation in the high-speed communication mode; and
when the lock signal for the retransmitted clock training pattern is not received within a predefined time, the low-speed communication mode is re-executed.
2 . The data processing device of claim 1 , wherein:
the clock training pattern is transmitted to enter the high-speed communication mode after the low-speed communication mode; and
the clock training pattern is retransmitted while maintaining the high-speed communication mode when a lock-fail signal is received during the transmission of image data after receiving a lock signal indicating completion of training for the clock training pattern.
3 . The data processing device of claim 1 , wherein:
when the low-speed communication mode is re-executed, a preamble pattern is retransmitted.
4 . The data processing device of claim 1 , wherein:
before retransmitting the clock training pattern, a recovery start signal is transmitted, and
the recovery start signal is a signal in which high and low levels are alternately repeated.
5 . The data processing device of claim 1 , wherein:
before retransmitting the clock training pattern, a recovery start signal is transmitted, and
the recovery start signal is a DC signal of either a high level or a low level.
6 . The data processing device of claim 1 , wherein:
when power is supplied, the low-speed communication mode is activated to transmit a preamble pattern, followed by transmitting the configuration data, and
when a lock signal for the preamble pattern is received, the configuration data is transmitted, and the high-speed communication mode is activated if the lock signal is continuously received.
7 . The data processing device of claim 1 , wherein:
when a lock signal for the clock training pattern is received, a link training pattern is transmitted.
8 . A data driving device, wherein the data driving device is configured to:
receive configuration data in a low-speed communication mode;
receive control data and image data in a high-speed communication mode after the low-speed communication mode; and
when a lock-fail is detected during operation in the high-speed communication mode, transmit a lock-fail signal to the data processing device, and perform training by receiving a recovery start signal and a clock training pattern while maintaining the high-speed communication mode;
when power is supplied, the low-speed communication mode is activated to receive a preamble pattern;
after a lock signal for the preamble pattern is transmitted, the configuration data is received; and
the high-speed communication mode is activated by continuously transmitting the lock signal.
9 . The data driving device of claim 8 , wherein:
the data driving device comprises a plurality of devices, and each data driving device includes a lock detector.
10 . A display device comprising:
a data processing device configured to transmit configuration data in a low-speed communication mode, to transition to a high-speed communication mode after the low-speed communication mode to transmit control data and image data, and to retransmit a recovery start signal and a clock training pattern while maintaining the high-speed communication mode when a lock-fail signal is received during the high-speed communication mode; and
a data driving device configured to receive the recovery start signal and the clock training pattern and perform training,
a first communication line configured to transmit the image data;
a second communication line configured to transmit and receive the lock signal; and
a third communication line configured to detect an interface connection between the data processing device and the data driving device,
wherein the data driving device is configured to change a signal level of at least one of the third communication line and the second communication line when a lock-fail signal is received while operating in the high-speed communication mode.
11 . The display device of claim 10 , wherein:
the data processing device transmits a clock training pattern to enter the high-speed communication mode after the low-speed communication mode; and
when a lock-fail signal is received during the transmission of image data after receiving a lock signal indicating completion of training for the clock training pattern, the data processing device retransmits the clock training pattern while maintaining the high-speed communication mode.
12 . The display device of claim 10 , wherein the data driving device maintains a signal level of the third communication line at a high level and changes a signal level of the second communication line to a low level when a lock-fail signal is received while operating in the high-speed communication mode.
13 . The display device of claim 10 , wherein the data driving device changes a signal level of the third communication line and a signal level of the second communication line to a low level when a lock-fail signal is received while operating in the high-speed communication mode.
14 . The display device of claim 10 , wherein the data driving device changes a signal level of the third communication line and a signal level of the second communication line to a low level when a lock-fail signal is received while operating in the low-speed communication mode.