Address decoder unit for a memory cell array using logic gates
An address decoder unit ( 30 ) for a memory cell array ( 10 ), the address decoder unit ( 30 ) including an address decoder ( 31 ) including an address input ( 33 ) and a number of address outputs ( 34, 35, 36 ), the address decoder ( 31 ) being operable to select one of the address outputs ( 34, 35, 36 ) in response to receive a memory address at the address input ( 33 ); and an address selection circuitry ( 32 ) connected to the address decoder ( 31 ) and including a number of address selection outputs ( 44, 45, 46 ) each of which connectable the memory cell array and each of which corresponding to one memory address, wherein the address decoder unit ( 30 ) is switchable into a memory erase mode, in which the address selection circuitry ( 32 ) is operable to select all address selection outputs ( 44, 45, 46 ) of an address space above or beyond a memory address provided at the address input ( 33 ).
1 . An address decoder unit ( 30 ) for a memory cell array ( 10 ), the address decoder unit ( 30 ) comprising:
an address decoder ( 31 ) comprising an address input ( 33 ) and a number of address outputs ( 34 , 35 , 36 ), the address decoder ( 31 ) being operable to select one of the address outputs ( 34 , 35 , 36 ) in response to receive a memory address at the address input ( 33 ), the one selected address output designating one memory cell among the memory cell array ( 10 ); and
an address selection circuitry ( 32 ) connected to an output of the address decoder ( 31 ) and comprising a number of address selection outputs ( 44 , 45 , 46 ) each of which connectable to the memory cell array ( 10 ) and each of which corresponding to one memory address designating one memory cell among the memory cell array ( 10 ),
wherein the address decoder unit ( 30 ) is switchable into a memory erase mode, in which the address selection circuitry ( 32 ) is operable to:
input the one address output selected by the address decoder ( 31 ), and
based on the one address output selected by the address decoder ( 31 ), select all address selection outputs ( 44 , 45 , 46 ) corresponding to memory addresses designating memory cells that are either above or below the memory address provided at the address input ( 33 ) of the address decoder ( 31 ).
2 . The address decoder unit ( 30 ) according to claim 1 , wherein the address selection circuitry ( 32 ) is further operable to unselect all address selection outputs ( 44 , 45 , 46 ) corresponding to memory addresses designating memory cells that are either below or above the memory address provided at the address input ( 33 ).
3 . The address decoder unit ( 30 ) according to claim 1 , wherein the address selection circuitry ( 32 ) comprises a number of logic gates ( 41 , 42 , 43 ) each of which comprising a first gate input ( 51 ), a second gate input ( 52 ) and a gate output ( 55 ), wherein each logic gate ( 41 , 42 , 43 ) is connected with two of the address selection outputs ( 44 , 45 , 46 ).
4 . The address decoder unit ( 30 ) according to claim 3 , wherein the first gate input ( 51 ) of a first logic gate ( 41 ) of the address selection circuitry ( 32 ) is connected to a first address output ( 34 ) of the address decoder ( 31 ), wherein the second gate input ( 52 ) of the first logic gate ( 41 ) is connected to a second address output ( 35 ) of the address decoder ( 31 ) and wherein the gate output ( 55 ) of the first logic gate ( 41 ) is connected to or forms a second address selection output ( 45 ) of the address selection circuitry ( 32 ).
5 . The address decoder unit ( 30 ) according to claim 4 , wherein a first gate input ( 51 ′) of a second logic gate ( 42 ) of the address selection circuitry ( 32 ) is connected to the gate output ( 55 ) of the first logic gate ( 42 ), wherein the second gate input ( 52 ′) of the second logic gate ( 42 ) is connected to a third address output ( 36 ) of the address decoder ( 31 ) and wherein the gate output ( 55 ′) of the second logic gate ( 42 ) is connected to or forms a third address selection output ( 46 ) of the address selection circuitry ( 32 ).
6 . The address decoder unit ( 30 ) according to claim 3 , wherein each logic gate ( 41 , 42 , 43 ) is operable to set its gate output ( 55 ) to a logic high level when at least one of the first gate input ( 51 ) and the second gate input ( 52 ) is at a logic high-level.
7 . The address decoder unit ( 30 ) according to claim 3 , wherein each one of the logic gates ( 41 , 42 , 43 ) comprises an enabling input ( 54 ) by way of which operation of the respective logic gate ( 41 , 42 , 43 ) can be activated or deactivated.
8 . The address decoder unit ( 30 ) according to claim 7 , wherein when a dedicated logic gate ( 41 , 42 , 43 ) of the number of logic gates ( 41 , 42 , 43 ) is deactivated, a gate output ( 55 ) of the dedicated logic gate ( 41 , 42 , 43 ) is at the same logic level than a second gate input ( 52 ) of the dedicated logic gate ( 41 , 42 , 43 ).
9 . The address decoder unit ( 30 ) according to claim 7 , wherein the enabling inputs ( 54 ) of the number of logic gates ( 41 , 42 , 43 ) are mutually connected.
10 . The address decoder unit ( 30 ) according to claim 3 , wherein at least one of the logic gates ( 41 , 42 , 43 ) comprises a logic AND gate ( 60 ) and a logic OR gate ( 70 ), wherein an output ( 73 ) of the logic OR gate ( 70 ) is connected to or forms the gate output ( 55 ) and wherein a first input ( 71 ) of the logic OR gate ( 70 ) is connected to an output ( 63 ) of the logic AND gate ( 60 ).
11 . The address decoder unit ( 30 ) according to claim 10 , wherein a second input ( 72 ) of the logic OR gate ( 70 ) is connected to the second gate input ( 52 ) of the logic gate ( 41 ) and wherein a first input ( 61 ) of the logic AND gate ( 60 ) is connected to the first gate input ( 51 ) of the logic gate ( 41 , 42 , 43 ).
12 . The address decoder unit ( 30 ) according to claim 7 , wherein a second input ( 62 ) of the logic AND gate ( 60 ) is connected to the enabling input ( 54 ).
13 . The address decoder unit ( 30 ) according to claim 1 , wherein the address decoder unit ( 30 ) is switchable into a memory read mode or memory write mode, in which the address selection circuitry ( 32 ) gates the address outputs ( 34 , 35 , 36 ) of the address decoder ( 31 ) to a corresponding address selection output ( 44 , 45 , 46 ).
14 . An electronic device comprising a memory cell array ( 10 ) and further comprising the address decoder unit ( 30 ) according to claim 1 connected to the memory cell array ( 10 ).
15 . A method of selecting numerous address selection outputs ( 44 , 45 , 46 ) of the address decoder unit ( 30 ) for the memory cell array ( 10 ) according to claim 1 , the method comprises the steps of:
providing an address decoder unit ( 30 ),
providing a memory address at the address input ( 33 ) of the address decoder ( 31 ),
generating and providing a memory selection signal on one of address outputs ( 34 , 35 , 36 ) of the address decoder ( 31 ) in response to receiving the memory address at the address input ( 33 ), the one address output designating one memory cell among the memory cell array ( 10 ),
inputting, by address selection circuitry ( 32 ) connected to an output of the address decoder ( 31 ), the memory selection signal on the one address output of the address outputs ( 34 , 35 , 36 ), and
based on the memory selection signal, selecting, by the address selection circuitry ( 32 ), all address selection outputs ( 44 , 45 , 46 ) corresponding to memory addresses designating memory cells that are either above or below the memory address provided at the address input ( 33 ).