Methods for controlling bit line voltages in memory devices
The present disclosure provides a method for controlling bit line voltages in a three-dimensional memory device. The method includes ramping up a bit line clamp regulation voltage and a control signal regulation voltage. The method also includes ramping up a bit line clamp enabling voltage and a control signal enabling voltage. The method also includes increasing a bit line clamp voltage in one stage, and increasing a control signal voltage in two stages. The method also includes decreasing the control signal voltage. The method also includes ramping down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage. The method further includes decreasing the bit line clamp voltage.
1 . A method for controlling bit line voltages in a three-dimensional memory device, comprising:
ramping up a bit line clamp regulation voltage and a control signal regulation voltage;
ramping up a bit line clamp enabling voltage and a control signal enabling voltage;
increasing a bit line clamp voltage in one stage, and increasing a control signal voltage in two stages;
decreasing the control signal voltage;
ramping down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage; and
decreasing the bit line clamp voltage,
wherein the bit line clamp regulation voltage, the bit line clamp enabling voltage, and the bit line clamp voltage, the control signal regulation voltage, and the control signal enabling voltage are each different bit line signals.
2 . The method of claim 1 , wherein:
the bit line clamp regulation voltage and the control signal regulation voltage are ramped up at a same first time point; and
the bit line clamp enabling voltage and the control signal enabling voltage are ramped up at a same second time point after the first time point.
3 . The method of claim 2 , wherein the ramping up the bit line clamp regulation voltage and the control signal regulation voltage comprises:
increasing the bit line clamp voltage and the control signal voltage from a low level at the second time point, and starting to increase the control signal voltage from an intermediate level at a third time point, such that the bit line clamp voltage and the control signal voltage reach their high levels respectively at a fourth time point.
4 . The method of claim 3 , wherein decreasing the control signal voltage comprises:
decreasing the control signal voltage to the low level before ramping down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage.
5 . The method of claim 4 , wherein ramping down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage, and decreasing the bit line clamp voltage comprises:
ramping down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage, and starting to decrease the bit line clamp voltage at a same fifth time.
6 . A method for controlling bit line voltages in a three-dimensional memory device, comprising:
generating a first voltage difference between a first bit line terminal and a second bit line terminal;
ramping up the first bit line terminal and the second bit line terminal by a second voltage difference, wherein the second voltage difference is different from the first voltage difference;
ramping up the first bit line terminal and the second bit line terminal by a third voltage difference, wherein the third voltage difference is different from the first and second voltage differences; and
repeating the ramping up the first bit line terminal and the second bit line terminal by the third voltage difference a plurality of times,
wherein the first voltage difference is formed based on a first pair of bit line signals and the second voltage difference is formed by a second pair of bit line signals different from the first pair.
7 . The method of claim 6 , wherein the generating the first voltage difference between the first bit line terminal and the second bit line terminal comprises:
increasing a first voltage to the first bit line terminal, and maintaining the second bit line terminal at a ground voltage level to form the first voltage difference between the first and second bit line terminals.
8 . The method of claim 6 , wherein the ramping up the first bit line terminal and the second bit line terminal by the second voltage difference comprises:
increasing the first and second bit line terminals with a pre-determined fixed value as the second voltage difference, such that the first and second bit line terminals substantially keep the first voltage difference.
9 . The method of claim 6 , wherein the ramping up the first bit line terminal and the second bit line terminal by the third voltage difference comprises:
increasing the first and second bit line terminals with the third voltage difference, such that the first and second bit line terminals substantially keep the first voltage difference.
10 . The method of claim 6 , wherein the repeating the ramping up the first bit line terminal and the second bit line terminal by the third voltage difference the plurality of times comprises:
repeating the ramping up the first bit line terminal and the second bit line terminal by the third voltage difference at least three times.
11 . A three-dimensional memory device, comprising:
a plurality of bit lines;
a peripheral circuit coupled to the plurality of bit lines and configured to provide voltages to the plurality of bit lines; and
a controller configured to control the peripheral circuit to:
ramp up a bit line clamp regulation voltage and a control signal regulation voltage,
ramp up a bit line clamp enabling voltage and a control signal enabling voltage,
increase a bit line clamp voltage in one stage, and increase a control signal voltage in two stages,
decrease the control signal voltage,
ramp down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage, and
decrease the bit line clamp voltage,
wherein the bit line clamp regulation voltage, the bit line clamp enabling voltage, and the bit line clamp voltage, the control signal regulation voltage, and the control signal enabling voltage are each different bit line signals.
12 . The memory device of claim 11 , wherein the peripheral circuit is further configured to:
ramp up the bit line clamp regulation voltage and the control signal regulation voltage at a same first time point; and
ramp up the bit line clamp enabling voltage and the control signal enabling voltage at a same second time point after the first time point.
13 . The memory device of claim 12 , wherein the peripheral circuit is further configured to:
start to increase the bit line clamp voltage and the control signal voltage from a low level at the second time point, and start to increase the control signal voltage from an intermediate level at a third time point, such that the bit line clamp voltage and the control signal voltage reach their high levels respectively at a same fourth time point.
14 . The memory device of claim 13 , wherein the peripheral circuit is further configured to:
decrease the control signal voltage to the low level before ramping down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage.
15 . The memory device of claim 14 , wherein the peripheral circuit is further configured to:
ramp down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage, and start to decrease the bit line clamp voltage at a same fifth time.
16 . The memory device of claim 11 , wherein the peripheral circuit is further configured to:
generate a first voltage difference between a first bit line terminal and a second bit line terminal,
ramp up the first bit line terminal and the second bit line terminal by a second voltage difference, and
ramp up the first bit line terminal and the second bit line terminal by a third voltage difference,
wherein the first, second and third voltage differences are different from each other.
17 . The memory device of claim 16 , wherein the peripheral circuit is further configured to:
increase a first voltage to the first bit line terminal, and maintain the second bit line terminal at a ground voltage level to form the first voltage difference between the first and second bit line terminals.
18 . The memory device of claim 16 , wherein the peripheral circuit is further configured to:
increase the first bit line terminal and the second bit line terminal by a pre-determined fixed voltage as the second voltage difference, such that the first and second bit line terminals substantially keep the first voltage difference.
19 . The memory device of claim 16 , wherein the peripheral circuit is further configured to:
repeating at least four times of increasing the first bit line terminal and the second bit line terminal by the third voltage difference, such that the first and second bit line terminals substantially keep the first voltage difference.
20 . The memory device of claim 16 , wherein:
the first voltage difference is in a range between about 0.25V and about 0.95V;
the second voltage difference is about 0.25V;
the third voltage different is a quarter of a difference between a target voltage of the second bit line terminal and 0.25V.