Detection and mitigation of attacks on row hammer mitigation circuits
Methods, apparatuses, and systems related to detecting and mitigating waterfall attacks are described. A memory device may include a waterfall attack mitigation circuit that is configured to detect, based on the ratio of read commands to write command received by the memory device, whether the memory device is the target of a waterfall attack. Upon detecting that the memory device is the target of a waterfall attack, the waterfall attack mitigation circuit can initiate certain mitigation actions, such as adjusting a threshold used to perform row hammer-related refreshes.
1 . A memory device, comprising:
a memory array including a plurality of rows of memory cells;
a row hammer mitigation circuit configured to:
determine whether a first row of the plurality of rows has accumulated an activation count exceeding a row hammer mitigation threshold, and
initiate, in response to determining that the first row has accumulated an activation count exceeding the row hammer mitigation threshold, a row hammer mitigation action; and
a waterfall attack mitigation circuit configured to:
calculate a read-to-write ratio characterizing a plurality of commands received by the memory device,
determine whether the calculated read-to-write ratio exceeds an expected read-to-write ratio representative of a waterfall attack that exploits row hammer effects through numerous activations of rows to cause an error in the memory device, and
initiate, in response to determining that the calculated read-to-write ratio exceeds the expected read-to-write ratio, a waterfall mitigation action.
2 . The memory device of claim 1 , wherein an activation count characterizes an activation directed to a row adjacent to the first row.
3 . The memory device of claim 1 , wherein the row hammer mitigation action comprises refreshing a row adjacent to the first row.
4 . The memory device of claim 1 , wherein calculating the read-to-write ratio comprises:
maintaining a count of read commands received by the memory device;
maintaining a count of write commands received by the memory device;
detecting a command received by the memory device;
determining whether the received command is a read command or a write command;
updating, based on the determination of whether the received command is a read command or a write command, the count of read commands or the count of write commands; and
generating the read-to-write ratio based on the count of read commands and the count of write commands.
5 . The memory device of claim 4 , wherein calculating the read-to-write ratio further comprises resetting the count of read commands to 0, and resetting the count of write commands to 0, after a threshold time has elapsed.
6 . The memory device of claim 5 , wherein the threshold time is between 1 ms and 2 ms.
7 . The memory device of claim 1 , wherein the calculated read-to-write ratio is based on commands received by the memory device during a 1 ms period of time.
8 . The memory device of claim 1 , the memory device further comprising:
a mode register configured to maintain the expected read-to-write ratio.
9 . The memory device of claim 8 , wherein the expected read-to-write ratio in the mode register is programmed by a host operatively coupled to the memory device.
10 . The memory device of claim 1 , wherein:
the memory array comprises a plurality of memory banks, each memory bank comprising a subset of the plurality of rows of memory cells; and
the waterfall mitigation circuit is further configured to:
maintain a plurality of read counters and write counters, wherein each of a read counter and a write counter are associated with a memory bank;
detecting a command received by the memory device, the command associated with a memory banks;
updating the read counter or write counter associated with the memory bank that is associated with the received command; and
wherein the calculated read-to-write ratio is associated with a memory bank, and calculated based on the read counter and write counter associated with the memory bank.
11 . The memory device of claim 1 , wherein the waterfall mitigation action comprises stalling the memory device.
12 . The memory device of claim 1 , wherein the waterfall mitigation action comprises lowering the row hammer mitigation threshold.
13 . The memory device of claim 1 , wherein the memory array is a DRAM array.
14 . A compute express link (CXL) card comprising:
a memory array; and
a controller configured to:
calculate a read-to-write ratio characterizing a plurality of commands received by the CXL card,
determine whether the calculated read-to-write ratio exceeds an expected read-to-write ratio representative of a waterfall attack that exploits row hammer effects through numerous activations of rows to cause an error in the memory device, and
initiate, in response to determining that the calculated read-to-write ratio exceeds the expected read-to-write ratio, a waterfall mitigation action.
15 . The CXL card of claim 14 , wherein the waterfall mitigation action comprises adjusting a row hammer mitigation threshold, based on which a subset of the memory array is refreshed.
16 . The CXL card of claim 14 , wherein calculating the read-to-write ratio comprises:
maintaining a count of read commands received by the CXL card;
maintaining a count of write commands received by the CXL card;
detecting a command received by the CXL card;
determining whether the received command is a read command or a write command;
updating, based on the determination of whether the received command is a read command or a write command, the count of read commands or the count of write commands; and
generating the read-to-write ratio based on the count of read commands and the count of write commands.
17 . The CXL card of claim 16 , wherein calculating the read-to-write ratio further comprises resetting the count of read commands to 0, and resetting the count of write commands to 0, after a threshold time has elapsed.
18 . The CXL card of claim 14 , wherein the expected read-to-write ratio is configured by a host operatively coupled to the CXL card.
19 . An apparatus comprising:
a memory array;
a row hammer mitigation circuit; and
a waterfall attack mitigation circuit configured to:
determine, based on a plurality of commands addressing the memory array, a waterfall attack targeting the memory array, wherein the plurality of commands corresponds to a pattern associated with a waterfall attack that exploits row hammer effects through numerous activations of rows to cause an error in the memory device, and
adjusting, based on the determination that a waterfall attack is targeting the memory array, a configuration of the row hammer mitigation circuit.
20 . The apparatus of claim 19 , wherein the configuration of the row hammer mitigation circuit comprises an activation threshold based on which a subset of memory array is refreshed.