Artificial intelligence processor and method of processing deep-learning operation using the same

1 . An Artificial Intelligence (AI) processor, comprising:

multiple Non-Volatile Memory (NVM) AI cores for respectively performing basic unit operations required for a deep-learning operation based on data stored in NVM;

on-chip memory for storing at least part of results of the basic unit operations; and

an AI core, separate from the multiple NVM AI cores, for performing an accumulation operation using the results of the basic unit operations,

wherein the AI core generates an expanded bit operation result using the accumulation operation, and

wherein the basic unit operation is an n-bit (n is a natural number) Multiply and Accumulation (MAC) operation, and the expanded bit operation result corresponds to 2*n bits.

2 . The AI processor of claim 1 , wherein:

part of the NVM AI cores and the AI core are power-gated depending on a bit width required for the deep-learning operation.

3 . The AI processor of claim 2 , wherein:

the bit width required for the deep-learning operation is set for each layer corresponding to the deep-learning operation.

4 . The AI processor of claim 1 , further comprising:

an AI DRAM controller for providing weights required for the basic unit operations to the NVM based on AI data stored in DRAM.

5 . The AI processor of claim 4 , wherein:

the AI DRAM controller reads features required for the basic unit operations from the DRAM and stores the features in the on-chip memory.

6 . The AI processor of claim 5 , wherein:

the AI DRAM controller stores only nonzero weights in the NVM.

7 . The AI processor of claim 6 , wherein:

the AI DRAM controller reads only features to be multiplied by nonzero weights from the DRAM.

8 . The AI processor of claim 7 , wherein:

the AI DRAM controller includes

a Direct Memory Access (DMA) unit for performing control for reading data from the DRAM and writing data to the DRAM;

a sparse weight unit for providing nonzero weight information to the DMA unit; and

a DRAM protocol converter for writing data to the DRAM or reading data from the DRAM based on control of the DMA unit.

9 . The AI processor of claim 1 , wherein:

each of the NVM AI cores includes

an NVM array; and

a MAC operator for performing a MAC operation based on data read from the NVM array.

10 . A method for processing a deep-learning operation, comprising:

performing, by respective multiple Non-Volatile Memory (NVM) AI cores, basic unit operations required for a deep-learning operation based on data stored in NVM;

storing at least part of results of the basic unit operations in on-chip memory;

performing, by an AI core, an accumulation operation using the results of the basic unit operations, the AI core being separate from the multiple NVM AI cores; and

storing a result of the accumulation operation in the on-chip memory,

wherein the AI core generates an expanded bit operation result by accumulating the results of the basic unit operations, and

wherein the basic unit operation is an n-bit (n is a natural number) Multiply and Accumulation (MAC) operation, and the expanded bit operation result corresponds to 2*n bits.

11 . The method of claim 10 , wherein:

part of the NVM AI cores and the AI core are power-gated depending on a bit width required for the deep-learning operation.

12 . The method of claim 11 , wherein:

the bit width required for the deep-learning operation is set for each layer corresponding to the deep-learning operation.

13 . The method of claim 10 , wherein:

the on-chip memory stores features required for the basic unit operations.

14 . The method of claim 13 , wherein:

the NVM stores only nonzero weights.