Semiconductor device
A product-sum calculation with high power efficiency is performed while maintaining a small area of a memory cell. A semiconductor device includes a memory cell array in which a plurality of memory cells are arranged in a matrix. Each memory cell of the plurality of memory cells includes a flip-flop circuit including two inverter circuits in each of which a load field effect transistor and a drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other, two transfer field effect transistors each having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the output portions of the two inverter circuits, and two resistance elements.
1 . A semiconductor device, comprising:
a memory cell array in which a plurality of memory cells are arranged in a matrix, wherein
each memory cell of the plurality of memory cells includes:
a flip-flop circuit including two inverter circuits, wherein
in each of the two inverter circuits, a load field effect transistor and a drive field effect transistor are connected in series, and
input portions of the two inverter circuits are cross-joined to output portions of the two inverter circuits;
two transfer field effect transistors, wherein
each of the two transfer field effect transistors has a gate electrode connected to a word line, and a pair of first and second main electrode regions, and
first main electrode regions of the pair of the first and second main electrode regions are respectively connected to the output portions of the two inverter circuits; and
two resistance elements, wherein
a first end side of each of the two resistance elements is connected to a respective second main electrode region of a corresponding one of the two transfer field effect transistors,
a second end side of each of the two resistance elements is respectively connected to a bit line and a bit line bar,
a resistance value of each of the two resistance elements is greater than a channel resistance value of each of the two transfer field effect transistors, and
each of the two resistance elements is in a low resistance state having a resistance sufficiently larger than that of the bit line and bit line bar, respectively, during a product-sum calculation.
2 . The semiconductor device according to claim 1 , wherein the resistance value of the two resistance elements is 1 MΩ or more.
3 . The semiconductor device according to claim 1 , wherein in a case where the product-sum calculation is executed, the word line is configured to function as an axon, the bit line is configured to function as a dendrite, and the bit line bar is configured to function as a dendrite bar.