Memory with double redundancy
A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.
1 . A memory, comprising:
a plurality of column groups, each column group in the plurality of column groups including a plurality of multiplexed columns, the plurality of column groups including a first column group and a second column group;
a first latch;
a second latch;
a first switch matrix coupled to the first column group, the second column group, the first latch, and the second latch;
a first redundant column group including a first plurality of multiplexed redundant columns; and
a second redundant column group including a second plurality of multiplexed redundant columns.
2 . The memory of claim 1 , further comprising:
a first decoder configured to decode an address signal to control a switching state of the first switch matrix responsive to a column redundancy state of the plurality of column groups.
3 . The memory of claim 2 , wherein the first switch matrix comprises:
a first switch coupled between the first column group and a first center node, a second switch coupled between the first center node and the second column group, a third switch coupled between the first latch and the first center node, and a fourth switch coupled between the first center node and the second latch.
4 . The memory of claim 2 , wherein each plurality of multiplexed columns comprises a plurality of multiplexed bit line pairs.
5 . The memory of claim 2 , wherein the first decoder includes a first logic gate configured to decode a first address signal.
6 . The memory of claim 5 , wherein the first decoder further includes a second logic gate configured to decode a second address signal.
7 . The memory of claim 6 , wherein the first logic gate and the second logic gate each comprises a NAND gate.
8 . The memory of claim 1 , wherein the first latch and the second latch each comprises an input latch for a write bit.
9 . The memory of claim 1 , wherein the first latch and the second latch each comprises an output latch for a read bit.
10 . The memory of claim 3 , wherein the first decoder is further configured to close the first switch and the third switch and to open the second switch and the fourth switch to couple the first latch to the first column group responsive to the plurality of column groups having no defective column group from an initial column group in the plurality of column groups to the first column group.
11 . The memory of claim 3 , wherein the first decoder is further configured to close the first switch and the fourth switch and to open the second switch and the third switch to couple the first latch to the second column group responsive to the first column group in the plurality of column groups being an initial defective column group.
12 . The memory of claim 3 , wherein the first decoder is further configured to open the first switch and the third switch and to close the second switch and the fourth switch responsive to the first column group being a second defective column group in the plurality of column groups.
13 . The memory of claim 3 , wherein the first switch and the second switch each comprises a transmission gate.
14 . The memory of claim 13 , wherein the third switch and the fourth switch each comprises a tri-state inverter.
15 . The memory of claim 3 , wherein the first switch, the second switch, the third switch, and the fourth switch each comprises a tri-state inverter.
16 . The memory of claim 3 , wherein the first decoder is further configured to decode the address signal to determine whether the first column group is in a no-shift region, a one-shift region, or a two-shift region.
17 . The memory of claim 1 , wherein the memory is integrated into a cellular telephone.
18 . The memory of claim 1 , wherein the memory is a static random-access memory (SRAM).