IP Library Granted Patent US 12665023
Granted Patent B2
US 12665023 · App. 18/628,554 · Granted Jun 23, 2026

Electronic device

Inventors: Ying-Chung Chen (Kaohsiung, TW); Shih-Chieh Tang (Kaohsiung, TW); Lu-Ming Lai (Kaohsiung, TW)
Assignee: Advanced Semiconductor Engineering, Inc.
G11C13/04G02B6/264
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Quick Facts
Patent No.
US 12665023
App. No.
18/628,554
Granted
Jun 23, 2026
Kind
B2
Abstract

An electronic device is provided. The electronic device includes a first photonic component, a memory module, and a plurality of processing units. The memory module includes a plurality of memory components supported by the first photonic component. The processing units are distributed at a periphery of the memory module, wherein the memory module is configured to be accessed by at least two of the processing units through the first photonic component.

Claims (37)

1 . An electronic device, comprising:

a first photonic component;

a memory module comprising a plurality of memory components supported by the first photonic component;

a plurality of processing units distributed at a periphery of the memory module, wherein the memory module is configured to be accessed by at least two of the processing units through the first photonic component;

a second photonic component electrically connected to at least one of the plurality of processing units and configured to optically couple to the first photonic component;

an optical component configured to provide a first optical source signal to the first photonic component and a second optical source signal to the second photonic component; and

an optical connector configured to actively optically align the first photonic component to the second photonic component to provide the second optical source signal to the second photonic component, wherein a distance between the optical connector and the first photonic component is less than a thickness of the optical connector.

2 . The electronic device of claim 1 , wherein each of the processing units is configured to access at least one of the memory components depending on a computing loading of the processing units.

3 . The electronic device of claim 1 , wherein when at least one of the processing units is not operated, all of the memory components are configured to be accessed by the other processing units that are operated, and none of the memory components becomes idle.

4 . The electronic device of claim 2 , wherein, when a first processing unit of the processing units having a higher computing loading than the other processing units, the first processing unit is configured to access the memory components that are most adjacent to the first processing unit.

5 . The electronic device of claim 1 , wherein the second photonic component is spaced apart from the first photonic component and comprises a conductive pillar passing through the second photonic component.

6 . The electronic device of claim 1 , wherein, in a cross-section, a height of the memory module is higher than a height of the first photonic component, and, in a top view, an area of the memory module is smaller than an area of the first photonic component.

7 . The electronic device of claim 1 , wherein the first photonic component is the only and single communication media for all of the processing units to access the memory module.

8 . The electronic device of claim 1 , wherein the optical component is disposed over the first photonic component and spaced apart from the second photonic component.

9 . The electronic device of claim 1 , wherein each of the processing units is configured to access at least one of the memory components depending on a required data volume of the processing units.

10 . The electronic device of claim 1 , wherein the first photonic component is configured as a centralized optical communication hub to allow each of the plurality of processing units distributed at the periphery to access the memory module.

11 . The electronic device of claim 9 , further comprising an electronic component configured to determine amounts of data stored in the memory components to be accessed by the processing units depending on a computing loading of the processing units, wherein the electronic component and the first photonic component collectively construct an optical engine.

12 . The electronic device of claim 11 , further comprising an electronic component is supported by the first photonic component, wherein the electronic component comprises a plurality of conductive pillars electrically connected to the memory module.

13 . The electronic device of claim 1 , further comprising a third photonic component spaced apart from the second photonic component and supporting at least one of the processing units, wherein a first distance between a first optical waveguide of the first photonic component and a second optical waveguide of the second photonic component is less than a second distance between the second optical waveguide of the second photonic component and a third optical waveguide of the third photonic component.

14 . The electronic device of claim 1 , wherein the optical connector comprises a lens structure which has a rectangular profile in a top view and has a curved profile in a cross-section.

15 . An electronic device, comprising:

a memory module comprising a plurality of memory components; and

a first processing unit disposed adjacent to the memory module, wherein the first processing unit comprises a first processing component and a second processing component configured to access different ones of the memory components through optical communication which is operated by the following:

a first photonic component supporting and electrically connected the memory module;

a second photonic component supporting and electrically connected to the first processing unit; and

an optical connector configured to passively optically align the first photonic component to the second photonic component, wherein a distance between the optical connector and the first photonic component is less than a thickness of the optical connector.

16 . The electronic device of claim 15 , wherein, in a cross-section, a height of the memory module is higher than a height of the first photonic component, and, in a top view, an area of the memory module is smaller than an area of the first photonic component.

17 . The electronic device of claim 16 , further comprising a third photonic component spaced apart from the second photonic component and a second processing unit supported by the third photonic component, wherein a first distance between a first optical waveguide of the first photonic component and a second optical waveguide of the second photonic component is less than a second distance between second optical waveguide of the second photonic component and a third optical waveguide of the third photonic component.

18 . An electronic device, comprising:

a carrier;

a memory module over the carrier; and

a plurality of processing units over the carrier, wherein the memory module is configured to be accessed by each of the processing units through optical communication which is operated by the following:

a first photonic component supporting and electrically connected the memory module;

a second photonic component supporting and electrically connected to at least one of the processing units; and

an optical connector configured to passively optically align the first photonic component to the second photonic component, wherein a distance between the optical connector and the first photonic component is less than a thickness of the optical connector.

19 . The electronic device of claim 18 , wherein the memory module is disposed over a center region of the carrier and comprises a plurality of memory stacks each comprising a plurality of memory components, the processing units comprise a first processing unit and a second processing unit configured to have a computing loading higher than that of the first processing unit, and a number of the memory stacks accessed by the second processing unit is greater than a number of the memory stacks accessed by the first processing unit, wherein the memory module is located between the first processing unit and the second processing unit.

20 . The electronic device of claim 18 , wherein, in a cross-section, a height of the memory module is higher than a height of the first photonic component, and, in a top view, an area of the memory module is smaller than an area of the first photonic component.