Memory, operation methods thereof and memory systems
Examples of the present application provide a memory, an operation method thereof and a memory system, and relate to, but are not limited to, the field of storage technology. The memory includes a peripheral circuit, a plurality of word lines and a plurality of rows of memory cells. Each row of the memory cells is coupled with one word line. The peripheral circuit is configured to apply a first voltage to a first word line of the plurality of word lines in each of a plurality of first time periods. A second voltage is applied to the first word line in a second time period between every two adjacent ones of the plurality of first time periods, wherein the second voltage is configured to turn on the memory cells coupled with the first word line. As such, the accuracy of data reading can be improved.
1 . A memory, comprising a peripheral circuit, a first word line, and a row of memory cells, the row of the memory cells coupled with the first word line, and the peripheral circuit is to:
apply a first voltage to the first word line in a first time period; and
apply a second voltage to the first word line in a second time period between two consecutive ones of the first time period, wherein a magnitude of the second voltage decreases after the two consecutive ones of the first time period, and wherein the second voltage is to turn on the row of memory cells coupled with the first word line.
2 . The memory of claim 1 , wherein the second voltage applied in second time periods are equal.
3 . The memory of claim 1 , wherein the peripheral circuit is to apply a pre-pulse voltage to the first word line before applying the first voltage, wherein the second voltage applied in the second time period is equal to the pre-pulse voltage.
4 . The memory of claim 1 , wherein the peripheral circuit is to apply a recovery pulse voltage to the first word line after applying the first voltage, wherein the second voltage applied in the second time period is equal to the recovery pulse voltage.
5 . The memory of claim 1 , wherein the first voltage is to read data of the row of memory cells coupled with the first word line.
6 . The memory of claim 1 , wherein the first voltage is to verify data of the row of memory cells coupled with the first word line during programming.
7 . The memory of claim 1 , wherein the first voltage increases sequentially.
8 . The memory of claim 1 , further including a second word line that is adjacent to the first word line, and the peripheral circuit is to:
apply a third voltage to the second word line in the first time period, wherein the third voltage is to turn on the row of memory cells coupled with the second word line; and
apply a fourth voltage to the second word line in the second time period, wherein the fourth voltage is less than the third voltage.
9 . The memory of claim 1 , further including a third word line that is not adjacent to the first word line, and the peripheral circuit is to apply a fifth voltage to the third word line in the first time period and the second time period, wherein the fifth voltage is to turn on the row of memory cells coupled with the third word line.
10 . A memory, comprising a peripheral circuit, word lines, and rows of memory cells, wherein the rows of memory cells are coupled to a word line of the word lines, and the peripheral circuit is to:
apply a first voltage to a first word line in a first time period; and
apply a second voltage to the first word line in a second time period between two consecutive ones of the first time period, wherein a magnitude of the second voltage decreases after the two consecutive ones of the first time period, and wherein second voltages applied in two of the second time periods are equal.
11 . The memory of claim 10 , wherein the second voltage applied in the second time period is greater than the first voltage.
12 . The memory of claim 10 , wherein the second voltage is to turn on a row of memory cells of the rows of memory cells coupled with the first word line.
13 . The memory of claim 10 , wherein the peripheral circuit is to apply a pre-pulse voltage to the first word line before applying the first voltage, wherein the second voltage applied in the second time period is equal to the pre-pulse voltage.
14 . The memory of claim 10 , wherein the peripheral circuit is to apply a recovery pulse voltage to the first word line after applying the first voltage, wherein the second voltage applied in the second time period is equal to the recovery pulse voltage.
15 . The memory of claim 10 , wherein the first voltage is to read data of a row of memory cells of the rows of memory cells coupled with the first word line.
16 . The memory of claim 10 , wherein the first voltage is to verify data of a row of memory cells of the rows of memory cells coupled with the first word line during programming.
17 . The memory of claim 10 , wherein the first voltage increases sequentially.
18 . The memory of claim 10 , wherein the word lines further include a second word line that is adjacent to the first word line, and the peripheral circuit is to:
apply a third voltage to the second word line in the first time period, wherein the third voltage is to turn on a row of memory cells of the rows of memory cells coupled with the second word line; and
apply a fourth voltage to the second word line in the second time period, wherein the fourth voltage is less than the third voltage.
19 . The memory of claim 10 , wherein the word lines further include a third word line that is not adjacent to the first word line, and the peripheral circuit is to apply a fifth voltage to the third word line in the first time period and the second time period, wherein the fifth voltage is to turn on a row of memory cells of the rows of memory cells coupled with the third word line.
20 . A memory system, comprising:
a controller, and
a memory comprising a peripheral circuit, word lines, and a row of memory cells, wherein the row of the memory cells is coupled to a word line of the word lines, and the peripheral circuit is to:
apply a first voltage to a first word line in a first time period; and
apply a second voltage to the first word line in a second time period between two consecutive ones of the first time period, wherein a magnitude of the second voltage decreases after the two consecutive ones of the first time period, and wherein the second voltage is to turn on the row of memory cells coupled with the first word line.