Memory device related to performing a program operation on memory cells

1 . A method for programming a plurality of memory cells, comprising:

applying program pulses of program voltages to a word line coupled to the plurality of memory cells during a plurality of program loops in a program operation for programming the plurality of memory cells to a plurality of program states;

determining a program speed of the plurality of memory cells;

adjusting, for remaining program loops of the program operation, at least one of a voltage level of the program pulses, an active time of the program pulses, a step voltage for the program pulses, and an offset for the program pulses based on the program speed; and

applying adjusted program pulses to the word line in the remaining program loops of the program operation.

2 . The method of claim 1 , further comprising:

generating an operation code based on the adjusting; and

generating the adjusted program pulses based on the operation code.

3 . The method of claim 1 , wherein the program speed of the plurality of memory cells is determined based on a number of program pulses until at least one of the plurality of memory cells reaches a reference threshold voltage.

4 . The method of claim 1 , wherein the program speed of the plurality of memory cells is determined based on whether a verify operation in the program operation satisfies a predetermined condition.

5 . The method of claim 1 , wherein the program speed of the plurality of memory cells is determined based on one of the plurality of program states except a lowest program state and a highest program state.

6 . A method for programming a plurality of memory cells, comprising:

applying program pulses of program voltages to a word line coupled to the plurality of memory cells during a plurality of program loops in a program operation for programming the plurality of memory cells to a plurality of program states;

determining a program speed of the plurality of memory cells;

adjusting at least one program pulse for remaining program loops of the program operation based on the program speed; and

applying the at least one adjusted program pulse to the word line in the remaining program loops of the program operation for varying the program speed of the plurality of memory cells.

7 . The method of claim 6 , wherein at least one of a voltage level, an active time and a step voltage of the at least one program pulse is changed by the adjusting.

8 . The method of claim 6 , wherein the program speed is determined based on verification data on the plurality of memory cells in the program operation.

9 . The method of claim 6 , wherein the program speed of the plurality of memory cells is determined based on one of the plurality of program states except a lowest program state and a highest program state.

10 . A method for programming a plurality of memory cells, comprising:

determining a program characteristic of the plurality of memory cells by applying a plurality of program pulses of program voltages to a word line coupled to the plurality of memory cells;

adjusting at least one program pulse based on the program characteristic; and

applying at least one adjusted program pulse to the word line for programming the plurality of memory cells.

11 . The method of claim 10 , wherein the program characteristic of the plurality of memory cells is a program speed determined based on threshold voltage increments of the plurality of memory cells as a plurality of program pulses are applied to the plurality of memory cells.

12 . The method of claim 11 , wherein the program speed of the plurality of memory cells is determined based on one of the plurality of program states except a lowest program state and a highest program state.

13 . The method of claim 11 , wherein at least one of a voltage level, an active time and a step voltage of the at least one program pulse is changed by the adjusting.

14 . A method for programming a plurality of memory cells, comprising:

receiving a program request for a program operation for programming the plurality of memory cells;

adjusting program pulses of program voltages based on a program characteristic of the plurality of memory cells; and

applying adjusted program pulses to a word line coupled to the plurality of memory cells in the program operation.

15 . The method of claim 14 , wherein the program characteristic of the plurality of memory cells is a program speed determined based on threshold voltage increments of the plurality of memory cells as a plurality of program pulses are applied to the plurality of memory cells.

16 . The method of claim 15 , wherein the program speed of the plurality of memory cells is determined based on a number of program pulses until at least one of the plurality of memory cells reaches a reference threshold voltage.

17 . The method of claim 14 , wherein at least one of a voltage level, an active time and a step voltage of the program pulses is changed by the adjusting.

18 . A method for programming a plurality of memory cells, comprising:

applying program pulses of program voltages to a word line coupled to the plurality of memory cells during a plurality of program loops in a first program operation for programming the plurality of memory cells to first program states;

determining a program characteristic of the plurality of memory cells in the first program operation;

adjusting program pulses of program voltages based on the program characteristic of the plurality of memory cells; and

applying adjusted program pulses to the word line coupled to the plurality of memory cells in a second program operation for programming the plurality of memory cells to second program states.

19 . The method of claim 18 , wherein a number of first program states is less than a number of second program states.

20 . The method of claim 19 , wherein the program characteristic of the plurality of memory cells is determined based on one of the first plurality of program states except a lowest program state.

21 . A method for programming a plurality of memory cells, comprising:

applying program pulses of program voltages to a word line coupled to the plurality of memory cells during a plurality of program loops in a program operation for programming the plurality of memory cells to a plurality of program states;

counting a number of program pulses until at least one of the plurality of memory cells reaches to a reference threshold voltage;

adjusting at least one program pulse for remaining program loops of the program operation based on a result of the counting; and

applying at least one adjusted program pulse to the word line in the remaining program loops of the program operation.

22 . The method of claim 21 , wherein at least one of a voltage level, an active time and a step voltage of the at least one program pulse is changed by the adjusting.

23 . A method for programming a memory block, comprising:

applying program pulses of program voltages to a word line coupled to a first memory cell group of the memory block during a plurality of program loops in a first program operation for programming the first memory cell group to a plurality of program states;

determining a program speed of the first memory cell group;

adjusting at least one of a voltage level of the program pulses, an active time of the program pulses, a step voltage for the program pulses, and an offset for the program pulses based on the program speed; and

applying adjusted program pulses to a next word line coupled to a second memory cell group of the memory block.