IP Library › Granted Patent US 12665040

Granted Patent B2

US 12665040 · App. 18/672,775 · Granted Jun 23, 2026

Memory device, memory system, and method of operating the same using bit line bias voltage scheme

Inventors: Chenhui Li (Wuhan, CN); Hongtao Liu (Wuhan, CN); Xiangnan Zhao (Wuhan, CN)

Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

G11C16/3459 G11C16/08 G11C16/102 G11C16/24

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Quick Facts

Patent No.: US 12665040
App. No.: 18/672,775
Granted: Jun 23, 2026
Kind: B2

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Abstract

A method of operating a memory device includes applying a first program voltage to a selected word line corresponding to a target group of memory cells, applying a first verify voltage to the selected word line corresponding to the target group of memory cells, applying a pre-determined number of program pulses to the selected word line corresponding to a second memory cell of the target group of memory cells, and applying a first bit line bias voltage to a first bit line corresponding to the second memory cell of the target group of memory cells during applying a first or a last of the pre-determined number of program pulses to the selected word line corresponding to the second memory cell.

Claims (52)

1 . A method of operating a memory device, comprising:

applying a first program voltage to a selected word line corresponding to a target group of memory cells, wherein the target group of memory cells comprises a first memory cell and a second memory cell, a target program state of the first memory cell is a first program state, and a target program state of the second memory cell is a second program state, wherein the memory cells in the second program state require a higher threshold voltage than those of the first program state to program, and each verify voltage corresponds to at least one program state;

applying a first verify voltage to the selected word line corresponding to the target group of memory cells;

applying a pre-determined number of program pulses to the selected word line corresponding to the second memory cell; and

applying a first bit line bias voltage to a first bit line corresponding to the second memory cell of the target group of memory cells during applying a first or a last of the pre-determined number of program pulses to the selected word line corresponding to the second memory cell.

2 . The method of claim 1 , further comprising:

based on cell information of the second memory cell, determining the first bit line bias voltage.

3 . The method of claim 1 , wherein:

the first bit line bias voltage is different from a first bit line voltage applied to the first bit line corresponding to the second memory cell of the target group of memory cells during applying the pre-determined number of program pulse other than the first or the last of the pre-determined number of program pulses to the selected word line corresponding to the second memory cell.

4 . The method of claim 1 , further comprising:

in response to that the first memory cell passes a first verification under the first verify voltage, inhibiting programming the first memory cell;

in response to that the second memory cell passes the first verification under the first verify voltage, applying the pre-determined number of program pulses to the selected word line corresponding to the second memory cell; and

inhibiting programming the second memory cell.

5 . The method of claim 1 , wherein applying a pre-determined number of program pulses to the selected word line corresponding to the second memory cell comprises:

applying n program pulse to the selected word line corresponding to the (n+1)th memory cell of the target group of memory cells, wherein n is an integer greater than 0.

6 . The method of claim 1 , wherein the first bit line bias voltage is a 3-bit-line (3BL) bias voltage, and wherein applying the first bit line bias voltage to the first bit line corresponding to the second memory cell of the target group of memory cells is during applying the last of the pre-determined number of program pulse to the selected word line corresponding to the second memory cell.

7 . The method of claim 6 , wherein the 3BL bias voltage is larger than 0V and smaller than 2.2V.

8 . The method of claim 1 , wherein applying the first bit line bias voltage to the first bit line corresponding to the second memory cell of the target group of memory cells is during applying the first of the pre-determined number of program pulse to the selected word line corresponding to the second memory cell.

9 . The method of claim 8 , wherein the first bit line bias voltage is larger than 0V and smaller than 2.2V.

10 . The method of claim 8 , wherein during applying the first of the pre-determined number of program pulses to the selected word line corresponding to the second memory cell, determining the first bit line bias voltage is based on:

determining that the first bit line corresponds to a first group of memory cells that are programmed faster than a second group of memory cells, wherein the target group of memory cells comprises the first group of memory cells and the second group of memory cells.

11 . A memory device, comprising:

a memory cell array comprising memory cells; and

a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to:

apply a first program voltage to a selected word line corresponding to a target group of memory cells, wherein the target group of memory cells comprises a first memory cell and a second memory cell, a target program state of the first memory cell is a first program state, and a target program state of the second memory cell is a second program state, wherein the memory cells in the second program state require a higher threshold voltage than those of the first program state to program, and each verify voltage corresponds to at least one program state;

apply a first verify voltage to the selected word line corresponding to the target group of memory cells;

apply a pre-determined number of program pulses to the selected word line corresponding to the second memory cell; and

apply a first bit line bias voltage to a first bit line corresponding to the second memory cell of the target group of memory cells during applying a first or a last of the pre-determined number of program pulses to the selected word line corresponding to the second memory cell.

12 . The memory device of claim 11 , wherein the peripheral circuit is further configured to:

based on cell information of the second memory cell, determine the first bit line bias voltage.

13 . The memory device of claim 11 , wherein:

14 . The memory device of claim 11 , wherein the peripheral circuit is further configured to:

in response to that the first memory cell passes a first verification under the first verify voltage, inhibiting programming the first memory cell;

inhibiting programming the second memory cell.

15 . The memory device of claim 11 , wherein the peripheral circuit configured to apply a pre-determined number of program pulses to the selected word line corresponding to the second memory cell is further configured to:

apply n program pulse to the selected word line corresponding to the (n+1)th memory cell of the target group of memory cells, wherein n is an integer greater than 0.

16 . The memory device of claim 11 , wherein the first bit line bias voltage is a 3-bit-line (3BL) bias voltage, and wherein the peripheral circuit is configured to apply the first bit line bias voltage to the first bit line corresponding to the second memory cell of the target group of memory cells during applying the last of the pre-determined number of program pulse to the selected word line corresponding to the second memory cell.

17 . The memory device of claim 16 , wherein the 3BL bias voltage is larger than 0V and smaller than 2.2V.

18 . The memory device of claim 11 , wherein the peripheral circuit is configured to apply the first bit line bias voltage to the first bit line corresponding to the second memory cell of the target group of memory cells during applying the first of the pre-determined number of program pulse to the selected word line corresponding to the second memory cell.

19 . The memory device of claim 18 , wherein during applying the first of the pre-determined number of program pulse to the selected word line corresponding to the second memory cell, the peripheral circuit is configured to determine the first bit line bias voltage based on:

20 . A memory system, comprising:

a memory device; and

a memory controller coupled to the memory device, wherein the memory device comprises:

a memory cell array comprising memory cells; and

a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to:

apply a first verify voltage to the selected word line corresponding to the target group of memory cells;

apply a pre-determined number of program pulse to the selected word line corresponding to the second memory cell; and

apply a first bit line bias voltage to a first bit line corresponding to the second memory cell of the target group of memory cells during applying a first or a last of the pre-determined number of program pulse to the selected word line corresponding to the second memory cell.