Memory sub-system threshold voltage modification operations
A method includes determining, for a plurality of memory dice, binning information relating to quality characteristics of each of the plurality of memory dice. The method further includes performing a select gate scan to determine a first threshold voltage and a first threshold voltage window of each of the plurality of memory dice, and, based on the determined quality characteristics of each of the plurality of memory dice, perform an erase and program operation to set a second threshold voltage with a second threshold voltage window of a subset of memory dice among the plurality of memory dice where the second threshold voltage window is greater than the first threshold voltage window.
1 . A method, comprising:
determining quality characteristics of each of a plurality of memory dice, wherein determining quality characteristics includes determining a first pair of threshold voltage distributions, including a first distribution corresponding to an erased state and a second distribution corresponding to a programmed state, and a first threshold voltage window of each of the plurality of memory dice, and wherein the first threshold voltage window is a difference in voltage between the first pair of threshold voltage distributions;
sorting the plurality of memory dice into a plurality of bins based on the respective first pairs of threshold voltage distributions and first threshold voltage windows; and
performing an erase and program operation to set a second pair of threshold voltage distributions, including a third distribution corresponding to a reduced erase state and a fourth distribution corresponding to an increased programmed state, with a second threshold voltage window for each memory die of a subset of the plurality of bins of memory dice that falls below a threshold reliability margin, wherein the second threshold voltage window is greater than the first threshold voltage window.
2 . The method of claim 1 , further comprising determining a reliability margin for each of the plurality of memory dice as part of determining the quality characteristics of each of the plurality of memory dice.
3 . The method of claim 1 , further comprising determining a high temperature data retention (HTDR) value of each of the plurality of memory dice.
4 . The method of claim 1 , wherein the second pair of threshold voltage distributions and the second threshold voltage window are the same for each subset of the plurality of bins of memory dice.
5 . The method of claim 1 , wherein performing the erase and program operation to set the second pair of threshold voltage distributions with the second threshold voltage window for each memory die of the subset of the plurality of bins of memory dice further comprises setting a first subset of memory dice and a second subset of memory dice to different second pairs of threshold voltage distributions, wherein the first subset of memory dice have the same second pair of threshold voltage distributions and second threshold voltage window and the second subset of memory dice have the same second pair of threshold voltage distributions and second threshold voltage window.
6 . The method of claim 5 , further comprising setting a third threshold voltage window to one of the first subset of memory dice or the second subset of memory dice, or both.
7 . An apparatus, comprising:
a memory device comprising a plurality of memory dice;
a processor coupled to the memory device, wherein the processor is configured to:
perform a select gate scan of each memory die of the plurality of memory dice;
determine quality characteristics of each of the plurality of memory dice, wherein determining quality characteristics includes determining a first pair of threshold voltage distributions, including a first distribution corresponding to an erased state and a second distribution corresponding to a programmed state, and a first threshold voltage window of each memory die of the plurality of memory dice based, at least in part, on the select gate scan of each memory die; and
perform an erase and program operation to set a second pair of threshold voltage distributions, including a third distribution corresponding to a reduced erase state and a fourth distribution corresponding to an increased programmed state, with a second threshold window of each memory die of the plurality of memory dice that falls below a threshold reliability margin.
8 . The apparatus of claim 7 , wherein the quality characteristics of each of the plurality of memory dice are based, at least in part, on a physical location of a wafer at which the memory dice were fabricated.
9 . The apparatus of claim 7 , wherein the quality characteristics of each of the plurality of memory dice are based, at least in part, on a Fuse ID corresponding to respective memory dice among the plurality of memory dice.
10 . The apparatus of claim 7 , wherein the processor is further configured to determine a reliability margin for each of the plurality of memory dice as part of determining the quality characteristics of each of the plurality of memory dice.
11 . The apparatus of claim 7 , wherein the processor is further configured to determine a high temperature data retention (HTDR) value of each of the plurality of memory dice.
12 . The apparatus of claim 7 , wherein the second pair of threshold voltage distributions and the second threshold voltage window are the same for each subset of memory dice among the plurality of memory dice.
13 . The apparatus of claim 7 , wherein performing the erase and program operation to set the second pair of threshold voltage distributions with the second threshold voltage window of each memory die of the plurality of memory dice the processor is further configured to set a first subset of memory dice of the plurality of memory dice and a second subset of memory dice of the plurality of memory dice to different second pairs of threshold voltage distributions, wherein the first subset of memory dice have the same second pair of threshold voltage distributions and second threshold voltage window and the second subset of memory dice have the same second pair of threshold voltage distributions and second threshold voltage window.
14 . A system, comprising:
a plurality of memory dice resident on a memory device;
a processor coupled to the plurality of memory dice, wherein the processor is configured to:
determine quality characteristics of each of a plurality of memory dice, wherein determining quality characteristics includes determining a first pair of threshold voltage distributions, including a first distribution corresponding to an erased state and a second distribution corresponding to a programmed state, and a first threshold voltage window of each memory die of the plurality of memory dice; and
perform an erase and program operation to set a second pair of threshold voltage distributions, including a third distribution corresponding to a reduced erase state and a fourth distribution corresponding to an increased programmed state, with a second threshold window of each memory die of the plurality of memory dice that falls below a threshold reliability margin, wherein the second threshold window is greater than the first threshold window.
15 . The system of claim 14 , wherein:
the system comprises testing circuitry,
the processor is resident on the testing circuitry, and
the memory device is couplable to the testing circuitry and the processor.
16 . The system of claim 14 , wherein:
system comprises testing circuitry,
the memory device is resident on the testing circuitry, and
the testing circuitry is couplable to the processor.
17 . The system of claim 14 , wherein the second pair of threshold voltage distributions and the second threshold voltage window are the same for each of the memory dice among the plurality of memory dice.
18 . The system of claim 14 , wherein the processor is further configured to determine, for the plurality of memory dice, binning information relating to quality characteristics of each of the plurality of memory dice.
19 . The system of claim 14 , wherein the processor is further configured to set a first subset of memory dice and a second subset of memory dice to different pairs of second threshold voltage distributions, wherein the first subset of memory dice have the same second pair of threshold voltage distributions and second threshold voltage window and the second subset of memory dice have the same pair of second threshold voltage distributions and second threshold voltage window.
20 . The system of claim 19 , wherein the processor is further configured to set a third threshold voltage window to one of the first subset of memory dice or the second subset of memory dice, or both.