Usage-based disturbance counter repair
Apparatuses and techniques for implementing usage-based disturbance (UBD) counter repair are described. In example implementations, a memory device includes multiple memory rows, multiple corresponding UBD counters, a register, and a spare UBD counter. If a UBD counter is faulty, logic can substitute the spare UBD counter. To do so, the logic can store a row address corresponding to the faulty UBD counter in the register. The logic can increment a value in the spare UBD counter responsive to a row activation corresponding to the stored row address. A mitigation procedure on a row that may be affected by the activation can be performed based on the value. A host device can control, at least partially, the UBD counter repair process. In these manners, a repair of a faulty UBD counter can be accomplished faster and/or with fewer resources as compared to replacing a memory row and corresponding UBD counter.
1 . An apparatus comprising:
a memory device comprising:
a memory array comprising multiple memory rows including a memory row corresponding to a memory row address;
multiple usage-based disturbance counters respectively associated with the multiple memory rows of the memory array, each respective usage-based disturbance counter of the multiple usage-based disturbance counters configured to count a respective quantity of at least one of accesses or activations of a respective memory row of the multiple memory rows of the memory array; and
usage-based disturbance counter repair circuitry coupled to the multiple usage-based disturbance counters, the usage-based disturbance counter repair circuitry comprising a register and a spare usage-based disturbance counter that can replace at least one usage-based disturbance counter of the multiple usage-based disturbance counters, the usage-based disturbance counter repair circuitry configured to:
store the memory row address in the register; and
update the spare usage-based disturbance counter responsive to an operation for the memory row corresponding to the memory row address stored in the register to replace a usage-based disturbance counter associated with the memory row while the memory row continues to be used to store data.
2 . The apparatus of claim 1 , wherein the usage-based disturbance counter repair circuitry is configured to:
compare a current memory row address for a current memory operation to the memory row address stored in the register;
responsive to the current memory row address being equal to the memory row address stored in the register, update the spare usage-based disturbance counter; and
responsive to the current memory row address being unequal to the memory row address stored in the register, update a usage-based disturbance counter of the multiple usage-based disturbance counters that corresponds to the current memory row address.
3 . The apparatus of claim 1 , wherein:
the usage-based disturbance counter repair circuitry is configured to assign different memory row addresses to the spare usage-based disturbance counter using the register; and
the memory device is configured to perform the operation for the memory row on the memory row in the memory array.
4 . The apparatus of claim 1 , wherein:
the operation for the memory row comprises an activation of the memory row corresponding to the memory row address stored in the register; and
the usage-based disturbance counter repair circuitry is configured to update the spare usage-based disturbance counter by incrementing a value stored in the spare usage-based disturbance counter responsive to the activation.
5 . The apparatus of claim 1 , wherein:
the operation for the memory row comprises at least one mitigation procedure performed on one or more memory rows affected by activations of the memory row corresponding to the memory row address stored in the register; and
the usage-based disturbance counter repair circuitry is configured to update the spare usage-based disturbance counter by clearing a value stored in the spare usage-based disturbance counter responsive to the at least one mitigation procedure.
6 . The apparatus of claim 1 , wherein the usage-based disturbance counter repair circuitry is configured to:
store another memory row address in the register in place of the memory row address, the other memory row address corresponding to another memory row of the multiple memory rows of the memory array;
clear the spare usage-based disturbance counter based on storage of the other memory row address in the register; and
update the spare usage-based disturbance counter responsive to another operation for the other memory row corresponding to the other memory row address stored in the register to replace another usage-based disturbance counter associated with the other memory row while the other memory row continues to be used to store data.
7 . The apparatus of claim 1 , wherein the memory device further comprises:
one or more mode registers comprising one or more bits relating to a repair capability for the multiple usage-based disturbance counters, the repair capability pertaining to the spare usage-based disturbance counter that is configured to be assignable to correspond to different memory row addresses.
8 . The apparatus of claim 7 , wherein the one or more bits of the one or more mode registers comprise:
at least one bit indicative of entry to or exit from a repair mode that enables the repair capability for the multiple usage-based disturbance counters using the spare usage-based disturbance counter.
9 . The apparatus of claim 1 , wherein the memory device further comprises:
usage-based disturbance counter operational circuitry configured to:
track at least one of accesses or activations of the multiple memory rows using the multiple usage-based disturbance counters; and
perform mitigation procedures on memory rows affected by the tracked accesses or activations.
10 . The apparatus of claim 1 , wherein:
each respective usage-based disturbance counter of the multiple usage-based disturbance counters corresponds to a respective memory row of the multiple memory rows of the memory array; and
each respective usage-based disturbance counter and each respective memory row form a respective combined memory row comprising data bits for the respective memory row and counter bits for the respective usage-based disturbance counter.
11 . The apparatus of claim 1 , wherein the usage-based disturbance counter repair circuitry is configured to:
detect that the usage-based disturbance counter of the multiple usage-based disturbance counters is faulty, the usage-based disturbance counter that is faulty corresponding to the memory row that corresponds to the memory row address.
12 . The apparatus of claim 11 , wherein the usage-based disturbance counter repair circuitry is configured to:
perform the storage of the memory row address in the register responsive to the detection by the memory device that the usage-based disturbance counter of the multiple usage-based disturbance counters is faulty.
13 . An apparatus comprising:
a memory device comprising:
an interface configured to be coupled to a host device; and
usage-based disturbance counter repair circuitry coupled to the interface and configured to:
receive from the host device a first command that relates to repairing a faulty usage-based disturbance counter using a spare usage-based disturbance counter configured to be assignable to different memory row addresses of multiple memory row addresses;
receive from the host device a second command that relates to the repairing of the faulty usage-based disturbance counter using the spare usage-based disturbance counter;
store in a register a memory row address of the multiple memory row addresses responsive to at least one of the first command or the second command, the memory row address corresponding to a memory row that is associated with the faulty usage-based disturbance counter, the faulty usage-based disturbance counter configured to count a quantity of at least one of accesses or activations of the memory row of multiple memory rows of a memory array; and
update the spare usage-based disturbance counter responsive to at least one of an access or an activation of the memory row corresponding to the memory row address stored in the register.
14 . The apparatus of claim 13 , wherein:
the spare usage-based disturbance counter is configured to be re-assignable to different memory row addresses of the multiple memory row addresses over time; and
the usage-based disturbance counter repair circuitry is configured to increment the spare usage-based disturbance counter responsive to the at least one of an access or an activation of the memory row corresponding to the memory row address stored in the register.
15 . The apparatus of claim 13 , wherein the usage-based disturbance counter repair circuitry is configured to:
write at least one bit in at least one mode register to enter a repair mode enabling a volatile repair of the faulty usage-based disturbance counter responsive to at least the first command.
16 . An apparatus comprising:
a host device comprising:
an interface configured to be coupled to a memory device; and
usage-based disturbance counter repair circuitry coupled to the interface and configured to:
transmit to the memory device a first command that relates to repairing a faulty usage-based disturbance counter using a spare usage-based disturbance counter that is configured to be assignable to multiple memory row addresses of multiple memory rows of a memory array of the memory device; and
transmit to the memory device a second command that relates to the repairing of the faulty usage-based disturbance counter using the spare usage-based disturbance counter,
at least one of the first command or the second command configured to cause the memory device to:
store in a register a memory row address of the multiple memory row addresses, the memory row address corresponding to a memory row that is associated with the faulty usage-based disturbance counter, the faulty usage-based disturbance counter configured to count a quantity of at least one of accesses or activations of the memory row of the multiple memory rows of the memory array of the memory device; and
update the spare usage-based disturbance counter responsive to at least one of an access or an activation of the memory row corresponding to the memory row address that is stored in the register.
17 . The apparatus of claim 16 , wherein the usage-based disturbance counter repair circuitry is configured to:
transmit to the memory device the first command to initiate the repairing of the faulty usage-based disturbance counter.
18 . The apparatus of claim 17 , wherein the usage-based disturbance counter repair circuitry is configured to:
transmit to the memory device the first command to write at least one bit in at least one mode register to enter a repair mode for the faulty usage-based disturbance counter.
19 . The apparatus of claim 18 , wherein the usage-based disturbance counter repair circuitry is configured to:
transmit to the memory device the second command to write to the at least one bit in the at least one mode register to exit the repair mode for the faulty usage-based disturbance counter.
20 . The apparatus of claim 17 , wherein the usage-based disturbance counter repair circuitry is configured to:
transmit to the memory device the second command including at least an indication of the memory row address to be assigned to the spare usage-based disturbance counter.