IP Library Granted Patent US 12665129
Granted Patent B2
US 12665129 · App. 18/140,978 · Granted Jun 23, 2026

Multilayered capacitor

Inventors: Sunghyung Kang (Suwon-si, KR); Hongje Choi (Suwon-si, KR); Oknam Kim (Suwon-si, KR)
Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
H01G4/012H01G4/30
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12665129
App. No.
18/140,978
Granted
Jun 23, 2026
Kind
B2
Abstract

A multilayered capacitor according to an embodiment includes a capacitor body including a dielectric layer and a first internal electrode layer and a second internal electrode layer stacked with the dielectric layer interposed therebetween, a first external electrode and a second external electrode on both sides of the capacitor body in the longitudinal direction, and 2n or more terminal electrodes on both sides of the capacitor body in a width direction. The first internal electrode layer includes n+1 first internal electrode patterns, the second internal electrode layer includes n second internal electrode patterns, and n is an integer greater than or equal to 1.

Claims (63)

1 . A multilayered capacitor, comprising

a capacitor body including a dielectric layer and a first internal electrode layer and a second internal electrode layer stacked with the dielectric layer interposed therebetween;

a first external electrode and a second external electrode on both sides of the capacitor body in a longitudinal direction; and

2n or more terminal electrodes on both sides of the capacitor body in a width direction,

wherein the first internal electrode layer includes n+1 first internal electrode patterns,

the second internal electrode layer includes n second internal electrode patterns,

n is an integer greater than or equal to 2, and

the remaining first internal electrode patterns, except for two first internal electrode patterns of the n first internal electrode patterns respectively connected to the first external electrode and the second external electrode, are spaced apart from the first external electrode, the second external electrode, and the 2n or more terminal electrodes.

2 . The multilayered capacitor of claim 1 , wherein

the n+1 first internal electrode patterns are disposed at intervals along the longitudinal direction, and

the first internal electrode layer has a division portion extending in the width direction between the n+1 first internal electrode patterns.

3 . The multilayered capacitor of claim 2 , wherein

an average length in the longitudinal direction of the division portion is greater than or equal to about 5 μm.

4 . The multilayered capacitor of claim 1 , wherein

one of the n+1 first internal electrode patterns is connected to the first external electrode, and another one of the n+1 first internal electrode patterns is connected to the second external electrode.

5 . The multilayered capacitor of claim 1 , wherein

one of the n second internal electrode patterns is connected to two or more of the 2n or more terminal electrodes.

6 . The multilayered capacitor of claim 5 , wherein

the two or more terminal electrodes connected to the one second internal electrode pattern are spaced apart from each other.

7 . The multilayered capacitor of claim 1 , wherein

one of the n second internal electrode patterns has two or more draw-out patterns connected to two or more of the 2n or more terminal electrodes.

8 . The multilayered capacitor of claim 7 , wherein

an average length in the longitudinal direction of the draw-out patterns is about 150 μm to about 250 μm,

an average length in the longitudinal direction of the terminal electrode is about 190 μm to about 500 μm.

9 . The multilayered capacitor of claim 1 , wherein

the n second internal electrode patterns are disposed at intervals along the longitudinal direction, and

the second internal electrode layer has a division portion extending in the width direction between the n second internal electrode patterns.

10 . The multilayered capacitor of claim 1 , wherein

the n second internal electrode patterns are configured to be overlapped with two or more of the n+1 first internal electrode patterns.

11 . The multilayered capacitor of claim 1 , wherein

the n+1 first internal electrode patterns have the same average length in the longitudinal direction, and

the n second internal electrode patterns have the same average length in the longitudinal direction.

12 . The multilayered capacitor of claim 1 , wherein

the n+1 first internal electrode patterns have different average lengths in the longitudinal direction, and

the n second internal electrode patterns have different average lengths in the longitudinal direction.

13 . A multilayered capacitor, comprising

a capacitor body including a dielectric layer and a first internal electrode layer and a second internal electrode layer stacked with the dielectric layer interposed therebetween;

a first external electrode and a second external electrode on both sides of the capacitor body in a longitudinal direction; and

a first terminal electrode to a fourth terminal electrode on both sides of the capacitor body in a width direction,

wherein the first internal electrode layer includes a 1-1 internal electrode pattern connected to the first external electrode, a 1-2 internal electrode pattern connected to the second external electrode, and a 1-3 internal electrode pattern disposed at intervals in the longitudinal direction between the 1-1 internal electrode pattern and the 1-2 internal electrode pattern,

the second internal electrode layer includes a 2-1 internal electrode pattern connected to the first terminal electrode and the second terminal electrode, and a 2-2 internal electrode pattern connected to the third terminal electrode and the fourth terminal electrode,

the 2-1 internal electrode pattern is configured to be overlapped with the 1-1 internal electrode pattern and the 1-2 internal electrode pattern, and

the 2-2 internal electrode pattern is configured to be overlapped with the 1-2 internal electrode pattern and the 1-3 internal electrode pattern.

14 . A multilayered capacitor, comprising

a capacitor body including a dielectric layer and a first internal electrode layer and a second internal electrode layer stacked with the dielectric layer interposed therebetween;

a first external electrode and a second external electrode on both sides of the capacitor body in a longitudinal direction; and

2n or more terminal electrodes on both sides of the capacitor body in a width direction,

wherein the first internal electrode layer includes n+1 first internal electrode patterns,

the second internal electrode layer includes n second internal electrode patterns,

n is an integer greater than or equal to 2,

each of the n second internal electrode patterns overlaps with two patterns among the n+1 first internal electrode patterns, and

one of the n+1 first internal electrode patterns is connected to the first external electrode, and another one of the n+1 first internal electrode patterns is connected to the second external electrode.

15 . The multilayered capacitor of claim 14 , wherein

the n+1 first internal electrode patterns are disposed at intervals along the longitudinal direction, and

the first internal electrode layer has a division portion extending in the width direction between the n+1 first internal electrode patterns.

16 . The multilayered capacitor of claim 15 , wherein

an average length in the longitudinal direction of the division portion is greater than or equal to about 5 μm.

17 . The multilayered capacitor of claim 14 , wherein

one of the n second internal electrode patterns is connected to two or more of the 2n or more terminal electrodes.

18 . The multilayered capacitor of claim 17 , wherein

the two or more terminal electrodes connected to the one second internal electrode pattern are spaced apart from each other.

19 . The multilayered capacitor of claim 14 , wherein

one of the n second internal electrode patterns has two or more draw-out patterns connected to two or more of the 2n or more terminal electrodes.