Layered pulse generation for laser driver application in 3D sensing
A layered pulse generator for a vertical-cavity surface-emitting laser (“VCSEL”) driver is disclosed consisting of three elements: a low-speed pulse generator, a high-speed pulse generator, and a pulse generator selector, all of which are on-chip with the VCSEL driver. By providing these elements on-chip, overall system power and complexity are reduced while allowing for significantly higher pulse train frequencies compared with known systems. The high-speed pulse generator is capable of generating pulses faster and with higher resolution than that of the low-speed pulse generator. The high-speed pulse generator uses multiple clock outputs, phase shifted, and synthesized into a single pulse waveform capable of wide-ranging frequencies, duty cycles and pulse counts.
1 . A circuit, comprising:
a VCSEL driver;
a pulse generator selector coupled to the VCSEL driver, the pulse generator selector adapted to receive a trigger signal, the trigger signal including a characteristic of a pulse train and being separate from the pulse train;
a first pulse generator coupled to the pulse generator selector;
a second pulse generator coupled to the pulse generator selector, the second pulse generator being a high-speed pulse generator adapted to provide the pulse train at a higher frequency than the first pulse generator, wherein;
the pulse generator selector is configured to, upon receiving the trigger signal, select one of the first and second pulse generators based upon the trigger signal and the characteristic to provide the pulse train to the VCSEL driver,
wherein the pulse generator selector is electrically connected between the first pulse generator and the VCSEL driver, the pulse generator selector is electrically connected between the second pulse generator and the VCSEL driver, and the pulse generator selector is adapted to selectively route the pulse train from the first pulse generator through the pulse generator selector to the VCSEL driver in a first selected configuration and selectively route the pulse train from the second pulse generator through the pulse generator selector to the VCSEL driver in a second selected configuration, the first and second selected configurations being different,
wherein the pulse generator selector is further configured to send a power-down signal to the second pulse generator in the first selected configuration and to send a power-down signal to the first pulse generator in the second selected configuration.
2 . The circuit of claim 1 , wherein the first pulse generator is a low-speed pulse generator adapted to generate the pulse train at a maximum speed lower than a maximum speed of the second pulse generator.
3 . The circuit of claim 1 , wherein an unselected one of the first and second pulse generators is configured to be powered down at a first time slot.
4 . The circuit of claim 1 , wherein the pulse generator selector is configured to generate a pulse for driving the VCSEL driver.
5 . The circuit of claim 4 , wherein the first and second pulse generators are configured to be powered down when the pulse generator selector generates the pulse for driving the VCSEL driver.
6 . The circuit of claim 1 , wherein the high-speed pulse generator comprises:
an oscillator adapted to generate multiple phase-shifted clocks; and
a pulse synthesizer adapted to select a plurality of clock pulses from the multiple phase-shifted clocks for generating a pulse synthesis waveform.
7 . The circuit of claim 6 , wherein the pulse synthesizer selects the plurality of clock pulses from the multiple phase-shifted clocks based on data regarding at least one of pulse width, pulse period, and pulse count.
8 . The circuit of claim 6 , wherein the oscillator is a ring oscillator.
9 . The circuit of claim 6 , wherein the pulse synthesizer selects the plurality of clock pulses from the multiple phase-shifted clocks based on at least one configuration setting, the at least one configuration setting including one or more of a pulse frequency, a duty cycle, a number of pulses per burst, a pulse width, a pulse period, a pulse count, and a triggering mode.
10 . The circuit of claim 1 , wherein the trigger signal is one of a SPI or I2C management interface.
11 . The circuit of claim 1 , wherein the trigger signal is received from a host chip using a digital pulse.
12 . The circuit of claim 1 , wherein the circuit is included in a time of flight sensor.
13 . The circuit of claim 1 , wherein the second pulse generator further includes:
an oscillator adapted to generate multiple phase-shifted clocks; and
a pulse synthesizer adapted to select a plurality of clock pulses from the multiple phase-shifted clocks for generating the pulse train of the second pulse generator, wherein the plurality of clock pulses are selected based on pre-determined parameters for the pulse synthesis waveform, including at least one of pulse width, pulse period, and pulse count.
14 . The circuit of claim 13 , wherein the circuit is included in a time of flight sensor.
15 . The circuit of claim 1 , wherein the characteristic includes at least one of: a pulse width, a pulse burst count, a duty cycle, and a pulse frequency.
16 . The circuit of claim 15 , wherein the characteristic includes the pulse frequency.