Electrostatic discharge protection device

1 . An electrostatic discharge protection device comprising:

a clamping bipolar junction transistor coupled between a first-voltage rail and a second-voltage rail; and

at least one electrostatic discharge circuit, coupled between the first-voltage rail and the second-voltage rail and coupled to an input/output (I/O) port, comprising:

a silicon-controlled rectifier with an anode thereof coupled to the I/O port, and a cathode of the silicon-controlled rectifier is coupled to the first-voltage rail; and

a diode with a cathode thereof coupled to the anode of the silicon-controlled rectifier and the I/O port, and an anode of the diode is coupled to the second-voltage rail;

wherein an absolute value of a reverse breakdown voltage of the diode is greater than an absolute value of an anode-to-cathode trigger voltage of the silicon-controlled rectifier and the absolute value of the anode-to-cathode trigger voltage of the silicon-controlled rectifier is greater than an absolute value of a trigger voltage of the clamping bipolar junction transistor;

wherein the silicon-controlled rectifier includes a parasitic PNP bipolar junction transistor and a parasitic NPN bipolar junction transistor and a base of the parasitic PNP bipolar junction transistor is decoupled to the I/O port.

2 . The electrostatic discharge protection device according to claim 1 , wherein the at least one electrostatic discharge circuit comprises a plurality of electrostatic discharge circuits.

3 . The electrostatic discharge protection device according to claim 1 , wherein the clamping bipolar junction transistor is an NPN bipolar junction transistor whose base is electrically floating, an NPN bipolar junction transistor whose emitter is coupled to its base, a PNP bipolar junction transistor whose base is electrically floating, or a PNP bipolar junction transistor whose emitter is coupled to its base.

4 . The electrostatic discharge protection device according to claim 1 ,

wherein the first-voltage rail is electrically floating.

5 . The electrostatic discharge protection device according to claim 1 , wherein the silicon-controlled rectifier comprises:

an N-type semiconductor substrate decoupled to the I/O port;

a first P-type well formed in the N-type semiconductor substrate;

a first P-type heavily-doped area and a first N-type heavily-doped area formed in the first P-type well and coupled to the first-voltage rail; and

a second P-type heavily-doped area formed in the N-type semiconductor substrate and coupled to the I/O port and the cathode of the diode, wherein the first P-type heavily-doped area, the first P-type well, the N-type semiconductor substrate, and the second P-type heavily-doped area form the parasitic PNP bipolar junction transistor, the first N-type heavily-doped area, the first P-type well, and the N-type semiconductor substrate form the parasitic NPN bipolar junction transistor, the clamping bipolar junction transistor and the diode are formed in the N-type semiconductor substrate, and the diode is formed between the clamping bipolar junction transistor and each of the first P-type well and the second P-type heavily-doped area;

wherein the diode comprises:

a second P-type well formed in the N-type semiconductor substrate; and

a second N-type heavily-doped area and a third P-type heavily-doped area formed in the second P-type well, wherein the second N-type heavily-doped area is coupled to the second P-type heavily-doped area and the I/O port and the third P-type heavily-doped area is coupled to the second-voltage rail;

wherein the clamping bipolar junction transistor comprises:

a third P-type well formed in the N-type semiconductor substrate; and

a third N-type heavily-doped area and a fourth N-type heavily-doped area formed in the third P-type well and respectively coupled to the second-voltage rail and the first-voltage rail.

6 . The electrostatic discharge protection device according to claim 5 , wherein a doping concentration of the third P-type well is greater than that of the first P-type well and a doping concentration of the first P-type well is greater than that of the second P-type well.

7 . The electrostatic discharge protection device according to claim 1 , further comprising a semiconductor substrate, at least one first isolation trench, and at least one second isolation trench, and the silicon-controlled rectifier comprises:

an N-type epitaxial layer formed on the semiconductor substrate, wherein the at least one first isolation trench and the at least one second isolation trench, formed in the N-type epitaxial layer and the semiconductor substrate, divides the N-type epitaxial layer into at least one first N-type epitaxial region, at least one second N-type epitaxial region, and a third N-type epitaxial region, the diode and the clamping bipolar junction transistor are respectively formed in the at least one second N-type epitaxial region and the third N-type epitaxial region, and the at least one first N-type epitaxial region is decoupled to the I/O port;

a first P-type well formed in the at least one first N-type epitaxial region;

a first P-type heavily-doped area and a first N-type heavily-doped area formed in the first P-type well and coupled to the first-voltage rail; and

a second P-type heavily-doped area formed in the at least one first N-type epitaxial region and coupled to the I/O port and the cathode of the diode, wherein the first P-type heavily-doped area, the first P-type well, the at least one first N-type epitaxial region, and the second P-type heavily-doped area form the parasitic PNP bipolar junction transistor, and the first N-type heavily-doped area, the first P-type well, and the at least one first N-type epitaxial region form the parasitic NPN bipolar junction transistor;

wherein the diode comprises:

a second P-type well formed in the at least one second N-type epitaxial region; and

a second N-type heavily-doped area and a third P-type heavily-doped area formed in the second P-type well, wherein the second N-type heavily-doped area is coupled to the second P-type heavily-doped area and the I/O port and the third P-type heavily-doped area is coupled to the second-voltage rail;

wherein the clamping bipolar junction transistor comprises:

a third P-type well formed in the third N-type epitaxial region; and

a third N-type heavily-doped area and a fourth N-type heavily-doped area formed in the third P-type well and respectively coupled to the second-voltage rail and the first-voltage rail.

8 . The electrostatic discharge protection device according to claim 7 , wherein a doping concentration of the third P-type well is greater than that of the first P-type well and a doping concentration of the first P-type well is greater than that of the second P-type well.

9 . The electrostatic discharge protection device according to claim 1 , further comprising a semiconductor substrate, at least one first isolation trench, and at least one second isolation trench, and the silicon-controlled rectifier comprises:

an N-type epitaxial layer formed on the semiconductor substrate, wherein the at least one first isolation trench and the at least one second isolation trench, formed in the N-type epitaxial layer and the semiconductor substrate, divides the N-type epitaxial layer into at least one first N-type epitaxial region, at least one second N-type epitaxial region, and a third N-type epitaxial region, the diode and the clamping bipolar junction transistor are respectively formed in the at least one second N-type epitaxial region and the third N-type epitaxial region, and the at least one first N-type epitaxial region is decoupled to the I/O port;

a first P-type well formed in the at least one first N-type epitaxial region;

a first P-type heavily-doped area and a first N-type heavily-doped area formed in the first P-type well and coupled to the first-voltage rail; and

a second P-type heavily-doped area formed in the at least one first N-type epitaxial region and coupled to the I/O port and the cathode of the diode, wherein the first P-type heavily-doped area, the first P-type well, the at least one first N-type epitaxial region, and the second P-type heavily-doped area form the parasitic PNP bipolar junction transistor, and the first N-type heavily-doped area, the first P-type well, and the at least one first N-type epitaxial region form the parasitic NPN bipolar junction transistor;

wherein the diode comprises:

a second P-type well formed in the at least one second N-type epitaxial region; and

a second N-type heavily-doped area and a third P-type heavily-doped area respectively formed in the at least one second N-type epitaxial region and the second P-type well, wherein the second N-type heavily-doped area is coupled to the second P-type heavily-doped area and the I/O port and the third P-type heavily-doped area is coupled to the second-voltage rail;

wherein the clamping bipolar junction transistor comprises:

a third P-type well formed in the third N-type epitaxial region; and

a third N-type heavily-doped area and a fourth N-type heavily-doped area formed in the third P-type well and respectively coupled to the second-voltage rail and the first-voltage rail.

10 . The electrostatic discharge protection device according to claim 9 , wherein a doping concentration of the third P-type well is greater than that of the first P-type well and a doping concentration of the first P-type well is greater than that of the second P-type well.