Signal power splitter/combiner with resistance and impedance transformer loading
An aspect relates to a signal power splitter/combiner including a first signal port; a first resistor; a first impedance transformer coupled in series with the first resistor between the first signal port and a first intermediate node; a second impedance transformer coupled between the first intermediate node and a second signal port; a third impedance transformer coupled between the first intermediate node and a third signal port; and a second resistor coupled between the second and third signal ports. The signal power splitter/combiner may further include a fourth impedance transformer coupled between the second impedance transformer and the second signal port, a fifth impedance transformer coupled between the third impedance transformer and the third signal port; and a third resistor coupled between a third intermediate nod.
1 . An apparatus, comprising:
a signal power splitter;
a first signal port;
a first resistor;
a first impedance transformer coupled in series with the first resistor between the first signal port and a first intermediate node, the first impedance transformer being between the first resistor and the first intermediate node, the first intermediate node coupled to the signal power splitter, wherein the first resistor and the first impedance transformer are configured to improve an impedance match or a return loss of the signal power splitter over a wider bandwidth; and
the signal power splitter, comprising:
a second impedance transformer having an input and an output, the first intermediate node being directly coupled to the input, and the output being coupled to a second signal port via a second intermediate node coupled between the output and the second signal port;
a third impedance transformer having an input and an output, the first intermediate node being directly coupled to the input, and the output being coupled to a third signal port via a third intermediate node coupled between the output and the third signal port; and
a second resistor coupled between the second and third signal ports;
wherein the first signal port is configured to receive a first input signal, and the first intermediate node is situated to split the first input signal to generate first and second output signals at the second and third signal ports, respectively.
2 . The apparatus of claim 1 , wherein the first impedance transformer comprises a first transmission line with a first impedance and a first length.
3 . The apparatus of claim 2 , wherein the second impedance transformer comprises a second transmission line with a second impedance and a second length.
4 . The apparatus of claim 3 , wherein the third impedance transformer comprises a third transmission line with a third impedance and a third length.
5 . The apparatus of claim 4 , wherein the second impedance is substantially the same as the third impedance, and wherein the second length is substantially the same as the third length.
6 . The apparatus of claim 1 , wherein the first impedance transformer comprises a first shunt capacitor, a first series inductor, and a second shunt capacitor, wherein the first and second shunt capacitors are coupled to both ends of the first series inductor, respectively.
7 . The apparatus of claim 6 , wherein the second impedance transformer comprises a third shunt capacitor, a second series inductor, and a fourth shunt capacitor, wherein the third and fourth shunt capacitors are coupled to both ends of the second series inductor, respectively.
8 . The apparatus of claim 7 , wherein the third impedance transformer comprises a fifth shunt capacitor, a third series inductor, and a sixth shunt capacitor, wherein the fifth and sixth shunt capacitors are coupled to both ends of the third series inductor, respectively.
9 . The apparatus of claim 8 , wherein the third, fourth, fifth, and sixth shunt capacitors have substantially the same capacitance, and wherein the second and third series inductors have substantially the same inductance.
10 . The apparatus of claim 6 , wherein the second impedance transformer comprises a second series inductor and a third shunt capacitor, wherein the second shunt capacitor is shared among the first and second impedance transformers, and wherein the second and third shunt capacitors are coupled to both ends of the second series inductor, respectively.
11 . The apparatus of claim 10 , wherein the third impedance transformer comprises a third series inductor and a fourth shunt capacitor, wherein the second shunt capacitor is shared among the first, second, and third impedance transformers, and wherein the second and fourth shunt capacitors are coupled to both ends of the third series inductor, respectively.
12 . The apparatus of claim 1 , further comprising:
a fourth impedance transformer having an input and an output, the input being directly coupled to the second intermediate node and the output being directly coupled to the second signal port, wherein the output of the second impedance transformer is directly coupled to the second intermediate node;
a fifth impedance transformer having an input and an output, the input being directly coupled to the third intermediate node and the output being directly coupled to the third signal port, wherein the output of the third impedance transformer is directly coupled to the third intermediate node; and
a third resistor coupled between the second and third intermediate nodes.
13 . The apparatus of claim 12 , wherein the fourth impedance transformer comprises a first transmission line with a first impedance and a first length, wherein the fifth impedance transformer comprises a second transmission line with a second impedance and a second length, wherein the first impedance is substantially the same as the second impedance, and wherein the first length is substantially the same as the second length.
14 . The apparatus of claim 12 , wherein:
the fourth impedance transformer comprises a first shunt capacitor, a first series inductor, and a second shunt capacitor, wherein the first and second shunt capacitors are coupled to both ends of the first series inductor, respectively;
the fifth impedance transformer comprises a third shunt capacitor, a second series inductor, and a fourth shunt capacitor, wherein the third and fourth shunt capacitors are coupled to both ends of the second series inductor, respectively; and
the first, second, third, and fourth shunt capacitors have substantially the same capacitance, and wherein the first and second series inductors have substantially the same inductance.
15 . A wireless communication device, comprising:
at least one antenna;
a set of transceiver chains coupled to the at least one antenna; and
a signal power splitter coupled to the set of transceiver chains;
a first signal port;
a first resistor;
a first impedance transformer coupled in series with the first resistor between the first signal port and a first intermediate node, the first impedance transformer being between the first resistor and the first intermediate node, the first intermediate node coupled to the signal power splitter, wherein the first resistor and the first impedance transformer are configured to improve an impedance match or a return loss of the signal power splitter does not include any additional signal path coupled to the first signal port; and
the signal power splitter comprising:
a second impedance transformer having an input and an output, the first intermediate node being directly coupled to the input, and the output being coupled to a second signal port via a second intermediate node coupled between the output and the second signal port;
a third impedance transformer having an input and an output, the first intermediate node being directly coupled to the input, and the output being coupled to a third signal port via a third intermediate node coupled between the output and the third signal port; and
a second resistor coupled between the second and third signal ports;
wherein the first signal port is configured to receive a first input signal, and the first intermediate node is situated to split the first input signal to generate first and second output signals at the second and third signal ports, respectively.
16 . The wireless communication device of claim 15 , wherein the first signal port is coupled to an input of a signal processing circuit, and wherein the second and third signal ports are coupled to inputs of the set of transceiver chains, respectively.
17 . The wireless communication device of claim 15 , wherein the second and third signal ports are coupled to outputs of the set of transceiver chains, respectively, and wherein the first signal port is coupled to an input of a signal processing circuit.
18 . The wireless communication device of claim 15 , wherein the signal power splitter further comprises:
a fourth impedance transformer having an input and an output, the input being directly coupled to the second intermediate node and the output being directly coupled to the second signal port, wherein the output of the second impedance transformer is directly coupled to the second intermediate node;
a fifth impedance transformer having an input and an output, the input being directly coupled to the third intermediate node and the output being directly coupled to the third signal port, wherein the output of the third impedance transformer is directly coupled to the third intermediate node; and
a third resistor coupled between the second and third intermediate nodes.
19 . The apparatus of claim 1 , wherein the first resistor includes a first resistance related to an impedance at the first signal port and a second resistance of the second resistor.
20 . The apparatus of claim 12 , wherein the first resistor includes a first resistance related to an impedance at the first signal port, a second resistance of the second resistor, and a third resistance of the third resistor.
21 . The apparatus of claim 12 , wherein the first resistor includes a first resistance related to a parallel resistance of the second and third resistors.
22 . The apparatus of claim 12 , wherein the first resistor includes a first resistance related to an impedance at the first signal port and a parallel resistance of the second and third resistors.
23 . The apparatus of claim 1 , wherein the first resistor and the first impedance transformer improve an impedance match between a first impedance at the first signal port and a second impedance at the first intermediate node.
24 . The apparatus of claim 1 , wherein:
the first resistor improves an impedance match between a first impedance at the first signal port and a second impedance at the first intermediate node at a first region of an operating frequency range of the signal power splitter; and
the first impedance transformer improves the impedance match between the first impedance at the first signal port and the second impedance at the first intermediate node at a second region of the operating frequency range of the signal power splitter, the second region being higher in frequency than the first region.