Monolithic-integrated bulk acoustic wave (BAW) resonator
Disclosed are techniques for an integrated circuit (IC) that includes one or more transistors on a substrate and an interconnection structure on the one or more transistors. The interconnection structure includes a semiconductor structure embedded in the interconnection structure. In an aspect, the semiconductor structure includes a cavity structure, a piezoelectric layer over the cavity structure, an upper conductive structure on the piezoelectric layer, and a first contact structure on the upper conductive structure. In an aspect, the cavity structure includes a bottom that is a part of a first etch stop layer over a substrate, a top that is a part of a second etch stop layer over the first etch stop layer, one or more sidewalls connecting the bottom and the top of the cavity structure, and a cavity between the top and the bottom of the cavity structure and surrounded by the one or more sidewalls.
1 . An integrated circuit (IC), comprising:
one or more transistors on a substrate; and
an interconnection structure on the one or more transistors, the interconnection structure including a plurality of interconnection layers, a plurality of interlayer dielectric layers, and a semiconductor structure embedded in the interconnection structure,
wherein the semiconductor structure comprises:
a cavity structure that includes:
a bottom that is a part of a first etch stop layer;
a top that is a part of a second etch stop layer over the first etch stop layer;
one or more sidewalls connecting the bottom and the top of the cavity structure; and
a cavity between the top and the bottom of the cavity structure and surrounded by the one or more sidewalls;
a piezoelectric layer over the cavity structure;
an upper conductive structure on the piezoelectric layer; and
a first contact structure on the upper conductive structure; and
wherein:
the upper conductive structure includes:
a first upper pattern portion over the cavity;
a first upper anchor portion coupled to the first upper pattern portion;
a vibration pattern over the cavity; and
multiple input/output terminals capacitively coupled with the vibration pattern,
the first upper pattern portion has an upper patch pattern or an upper finger pattern,
the first contact structure is coupled to the first upper anchor portion,
the semiconductor structure comprises multiple contact structures that include the first contact structure, and
the multiple contact structures are coupled to the multiple input/output terminals, respectively.
2 . The IC of claim 1 , further comprising:
an acoustic reflecting structure over the upper conductive structure.
3 . The IC of claim 2 , wherein the acoustic reflecting structure includes layers of refractory materials, and the refractory materials include tungsten, titanium, tantalum oxide, or any combination thereof.
4 . The IC of claim 1 , wherein:
the upper conductive structure further includes:
a second upper pattern portion over the cavity without overlapping the first upper pattern portion; and
a second upper anchor portion coupled to the second upper pattern portion, and
the semiconductor structure further comprises a second contact structure that is coupled to the second upper anchor portion.
5 . The IC of claim 1 , wherein the piezoelectric layer includes aluminum nitride, aluminum scandium nitride, or any combination thereof.
6 . The IC of claim 1 , wherein the top, the bottom, and the one or more sidewalls of the cavity structure include silicon nitride.
7 . The IC of claim 1 , wherein the cavity structure further comprises:
an intermediate etch stop layer; and
a dielectric layer between the top of the cavity structure and the intermediate etch stop layer,
wherein the cavity is between the intermediate etch stop layer and the bottom of the cavity structure.
8 . The IC of claim 1 , wherein the interconnection structure further comprises a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor in one of the plurality of interlayer dielectric layers, wherein the one of the plurality of interlayer dielectric layers is on the second etch stop layer.
9 . A method of manufacturing an integrated circuit (IC), comprising:
forming one or more transistors on a substrate; and
forming an interconnection structure on the one or more transistors, the interconnection structure including a plurality of interconnection layers, a plurality of interlayer dielectric layers, and a semiconductor structure embedded in the interconnection structure, the forming the interconnection structure comprising:
forming a piezoelectric layer over a first etch stop layer and a second etch stop layer, the first etch stop layer being over the substrate, and the second etch stop layer being over the first etch stop layer;
forming an upper conductive structure on the piezoelectric layer;
forming a cavity structure after the upper conductive structure is formed, the cavity structure including:
a bottom that is a part of the first etch stop layer;
a top that is a part of the second etch stop layer;
one or more sidewalls connecting the bottom and the top of the cavity structure; and
a cavity between the top and the bottom of the cavity structure and surrounded by the one or more sidewalls; and
forming a first contact structure on the upper conductive structure, wherein:
the forming the upper conductive structure includes patterning an upper conductive layer to become the upper conductive structure that includes:
a first upper pattern portion over the cavity;
a first upper anchor portion coupled to the first upper pattern portion;
a vibration pattern over the cavity; and
multiple input/output terminals capacitively coupled with the vibration pattern,
the first upper pattern portion has an upper patch pattern or an upper finger pattern,
the first contact structure is coupled to the first upper anchor portion,
the semiconductor structure comprises multiple contact structures that include the first contact structure, and
the multiple contact structures are coupled to the multiple input/output terminals, respectively.
10 . The method of claim 9 , wherein the forming the cavity structure comprises:
forming one or more first openings through the second etch stop layer and an interlayer dielectric layer between the first etch stop layer and the second etch stop layer, the one or more first openings exposing a portion of the first etch stop layer;
forming a third etch stop layer over the upper conductive structure;
at least partially filling the one or more first openings with an etch stop material to form the one or more sidewalls;
forming one or more second openings through the second etch stop layer, the one or more second openings being within an inner region defined by the one or more sidewalls; and
performing an etching process based on moving an etchant through the one or more second openings to remove a portion of the interlayer dielectric layer that is within a region defined by the bottom, the top, and the one or more sidewalls.
11 . The method of claim 10 , wherein the forming the cavity structure further comprises:
sealing the one or more second openings with the etch stop material.
12 . The method of claim 10 , wherein the forming the third etch stop layer and the at least partially filling the one or more first openings are based on a same deposition process.
13 . The method of claim 10 , wherein the forming the one or more second openings is based on an anisotropic etching process.
14 . The method of claim 9 , wherein the forming the interconnection structure further comprises: forming an acoustic reflecting structure over the upper conductive structure.
15 . The method of claim 14 , wherein the acoustic reflecting structure includes layers of refractory materials, and the refractory materials include tungsten, titanium, tantalum oxide, or any combination thereof.
16 . The method of claim 9 , wherein the piezoelectric layer includes aluminum nitride, aluminum scandium nitride, or any combination thereof.
17 . The method of claim 9 , wherein the forming the interconnection structure further comprises forming a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor in one of the plurality of interlayer dielectric layers, wherein the one of the plurality of interlayer dielectric layers is on the second etch stop layer.
18 . The method of claim 9 , wherein:
the forming the upper conductive structure includes the patterning the upper conductive layer to become the upper conductive structure that further includes:
a second upper pattern portion over the cavity without overlapping the first upper pattern portion; and
a second upper anchor portion coupled to the second upper pattern portion, and
the method further comprises forming a second contact structure that is coupled to the second upper anchor portion.